This blog explains the using the A2DP sink example in WICED. The I2S Configuration requirements and hardware interfacing.
Tool: WICED Studio 6.1 or above, A2DP Source (Cell Phone), DAC/Codec Breakout or Shields, Loudspeaker or Headphones.
Programming Language: C
Associated Parts: CYW20706
Related Hardware: CYW920706WCDEVAL, CYBT-343026-EVAL
A2DP Sink is a ready example project in WICED Studio. It has all the necessary code written to test the functionality. It has capability to establish the connection and route the Audio Stream coming from the A2DP Source via BT to the I2S block which needs to connect to an Audio DAC / Codec to reproduce the sound on a Loudspeaker / Headphones.
Looking at the code one might see codec configuration and get confused with the I2C Codec configuration. BT Audio there are 2 codecs.
The A2DP sink example is located at 'apps/snip/bt/a2dp_sink'.
BLCK / PCM_CLK
Word Select / Left Right Control.
Audio Data In
DO / PCM_OUT
Audio Data Out
The I2S is a simple full duplex serial interface, the data on the DI /DO pins is sampled at the BCLK edge. WS/LRC simply indicates if the data on DI/DO is for Left or Right channel of audio. The frequency of this signal indicates the selected Audio Sampling Rate. Refer the codec datasheets for timing diagrams, register configuration.
I2S in CYW20706:
I2S Mode: Master Mode (Codec is Slave)
Sample Rate: 44.1Khz or 48Khz (set based on the capabilities of the A2DP Source)
Data width: 16 bits for each Channel.
Bit CLK: Sample Rate * Data Width. Uses internal ACLK to generate this)
I2S – DI
J22 – Pin 7
J4 – Pin 2
I2S – DO
J22 – Pin 8
J4 – Pin 1
I2S – BCLK
J22 – Pin 5
J7 – Pin 2
I2S – WS / LRC
J22 – Pin 6
J4 – Pin 5
Fig1: Wiring Example CYW920706WCDEVAL1 + Adafruit MAX98357 I2S Class D Mono AMP
The onboard User button SW3 shares a pin with WS/LRC signal. To run the code correctly 2 changes are needed.
Choosing an I2S Codec:
Any codec that can support 16bit Audio at 44.1Kz or 48Khz sample rate will work. Audio Codec’s support configuration of the I2S parameters like Data Width, Sample rate etc. over I2C and some over SPI as well. As an example, WM8731 by default is set up for a 24bit data, but can be changed to 16bit by modifying a register configuration of the WM8731 through the I2C / SPI control interface.
MCLK (Master clock) is another important signal. Some codecs generate this internally, other need a TTL or Crystal oscillator. The frequency for MCLK is dependent on the Audio Sample rate, refer the codec datasheet to make sure the correct frequency is provided.
Due to Pin Multiplexing limitations on the CYW920706WCDEVAL & CYBT-343026-EVAL, the I2C pins are not free when I2S is in use. A Codec with SPI interface for configuration would be needed if the default configuration does not match.