I have the following questions about register settings.
I would appreciate it if you could leave me a comment.
1. Set Reg34[2:0] to 7 to start the ADC and clear when read later.
Is it a specification that Reg34[2:0] is cleared when it goes around the PRT?
2. I think that the main controller internally uses ADC to judge TDET and PDET, but in order to read Reg40, Reg41 (ADC result) in SPI communication, ADC is started with Reg34[2:0] can you tell me why?
3. I think that ADC is stopped when Reg34[2:0] is 0, but why does DIV_O, which indicates ADC start, appear periodically?
4. Why does DIV_O not occur unless 2D or 3D is written to Reg8[3:2]?
1. As soon as the pulse is finished, the sensor ADC is started, and the IF signals are converted and evaluated by the digital detector and the adc_result_ready bit within GSR0 is cleared by reading any of the result registers (Reg38-Reg53).
2. The digital detector judges the TDET and PDET using ADC data. In order to get the result from the ADC result registers, the ADC should be enabled first which is Reg34[2:0].
Please be remembered that enabling of the ADC is not allowed before the bandgap_up flag (Reg36) is readout as high. The bandgap is enabled by setting the bandgap_en bit (Reg34). This can be done simultaneously with adc_clk_en (Reg34). The bandgap can be enabled or disabled independently of all other parts of the ADC.
3. DIV_O is just the output of frequency divider. Irrespective of the ADC the clock sustains in the system. It depends on which value is selected at the div_sel.
4. Setting div_out_en provides the divided output frequency from
the VCO to Div_O pad based on div_sel value. By Default: 0D
Selects frequency divider setting. In default state internal 9.6
MHz clock is selected.
Note: Setting ADC is not a necessary step to do in SPI pulsed mode, the ADC of I&Q is triggered by the device internal state machine. Thus, the I&Q signals are sampled by the internal detector, so you just need to read the ADC registers Reg40 & Reg41 for I&Q signals respectively.
Refer this link for more information: https://community.infineon.com/t5/Radar-sensor/BGT60LTR11AIP-SPI-Communication/td-p/376372
1. When we write "3" to Reg34[2:0] experimentally and immediately read it twice in succession (within 30usec), the second time is cleared. What are the conditions to be cleared?
I'm trying to set adc_en after making sure the bandgap_up flag (Reg36) is high, but it can't be set if it's cleared. What conditions can be set?
Also, can't the ADC be enabled before the bandgap_up flag (Reg36) is read as high?
Do I have to write Reg35[15:0] if I synchronize to DIV_O and retry the ADC every time?
Is it NG even if the DIV_O state (Low/High) is Waited?
Could you please comment on the procedure?
2. The digital detector uses the ADC data to determine TDET and PDET, but if the ADC is not started with Reg34[2:0], what results does the digital detector determine?
3. Thank you for you surport.
4. Writing 0D to Reg8[3:2] will not output DIV_O. Can you give me some advice?
Is there any sample source code for register control related to ADC processing in SPI mode?
I’m so sorry for the rush.
Can you answer these questions ASAP?
Sorry for the delayed response!
In SPI pulsed mode, the ADC of I&Q is triggered by the device internal state machine. Thus, the I&Q signals are sampled by the internal detector, so you just need to read the ADC registers Reg40 & Reg41 for I&Q signals respectively.
In SPI CW mode, you need to enable internal ADC manually, by doing the following:
enable bandgap and local ADC clock (Reg34)
wait until bandgap is available (Reg36)
enable ADC (Reg34)
wait until ADC is ready (Reg36)
The ADC cannot be enabled unless bandgap_up flag (Reg36) is read as high.
You need not write to Reg35[15:0] to synchronize DIV_O, write access to Reg35 starts ADC conversion with the selected settings.
When RF blocks are switched on, the detector can be activated. It takes another 50 ms after enabling of
detector for settling of baseband. During this time the outputs TDet and PDet are kept in inactive state.
you will get output at DIV_O only when div_sel is written 1d, 2d or 3d. Setting div_out_en provides the divided output frequency from the VCO to Div_O pad based on div_sel value. The div_sel value
of “0” is not applicable.
There isn't any sample source code for register control related to ADC processing in SPI mode. You will be able to get the results by following the steps mentioned above.
Thank you for your advice.
I got ADC control.
I got a temperature sensor on CH12. The value will be 119.
Is this value in °F? If yes, the temperature value is about 48℃,is it correct?
If not , I want to convert to ℃, so please comment to us.
>In SPI pulsed mode, the ADC of I&Q is triggered by the device internal state machine. Thus, the >I&Q signals are sampled by the internal detector, so you just need to read the ADC registers Reg40 & >Reg41 for I&Q signals respectively.
We can read the value from Reg40 & Reg41, can you tell us the conversion formula?
>As the ADC is physically an 8-bit ADC also bit 0 and bit 1 are not used.
Since the number of effective bits is 8bit, I think that Max will be 255.
I think the Max temperature is below 1°C. (255 x 0.001 = 0.255°C)
Do you have calculation specifications?
As of now we do not do any further calculation based on any formula.
You need only to read the 8bit MSB of the ADC Result registers REG38-53.
Our team is looking into this to provide you with appropriate information to your queries.
The temperature can be calculated with the formula shown below:
Please be noted that this is used for internal reliability testing. This may not give you the accurate results of temperature.