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nDonnelly
Level 3
Level 3
10 questions asked 25 sign-ins 10 replies posted

Hi, I have designed a board using the BGT60LTR11AIP motion sensor in SPI mode using XMC, I have set up registers like the example provided in REF BGT60LTR11AIP MO firmware, however I am having issues with the pulse on time. When checking BGT DIV OUT on the scope I get the expected results for both 5us and 10 us, however when I try to set it as 20us or 40us it fails and the pulse remains on for less than 5us, do you have an explanation for this? Note the PRT works for each register value

 

Also could you explain why in REF BGT60LTR11AIP MO in acquisition.c in function aqusistion_init() the need for skip enable and skip flag when the pulse on time is set to 40us

 

Lastly in the ADC interrupt you disable the event generator trigger however it is not enabled again 

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Siddharth_H
Moderator
Moderator
Moderator
250 replies posted 100 solutions authored 50 likes received

Hello @nDonnelly ,

 

1) This should be happening because you are using the default capacitance values for you S&H circuit that is 5.6nF. So with this capacitance value 20us and 40us PW is not possible, instead you will have to use a 56nF cap for 40us PW to be possible. Refer to 3.5:External capacitors of the application note AN608.

 

2) Here, we check on BGT_DIV_TRG_IN falling edge signal to start ADC sampling. For PW: 40us, PRT: 500us (8% duty-cycle) we get 2 pulses meaning 2 falling edges.

First falling edge has to be skipped, since pulse is still turned ON. 2nd falling edge is taken into consideration, since pulse is here OFF, to trigger the ADC so is why we skip every alternate trigger.

 

3) ADC interrupt event generator trigger is disabled because here we use BGT_DIV_TRG_IN for the trigger.

 

Thanks,

Siddharth.

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Siddharth_H
Moderator
Moderator
Moderator
250 replies posted 100 solutions authored 50 likes received

Hello @nDonnelly ,

 

1) This should be happening because you are using the default capacitance values for you S&H circuit that is 5.6nF. So with this capacitance value 20us and 40us PW is not possible, instead you will have to use a 56nF cap for 40us PW to be possible. Refer to 3.5:External capacitors of the application note AN608.

 

2) Here, we check on BGT_DIV_TRG_IN falling edge signal to start ADC sampling. For PW: 40us, PRT: 500us (8% duty-cycle) we get 2 pulses meaning 2 falling edges.

First falling edge has to be skipped, since pulse is still turned ON. 2nd falling edge is taken into consideration, since pulse is here OFF, to trigger the ADC so is why we skip every alternate trigger.

 

3) ADC interrupt event generator trigger is disabled because here we use BGT_DIV_TRG_IN for the trigger.

 

Thanks,

Siddharth.

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