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I use this hub , but I do not use EEPROM. In datasheet i saw next :
" After reading the EEPROM, if VBUSPOWER (connected to up-stream VBUS) is high, CY7C65621/31 enables the pull up resistor on D+ to indicate its presence to the upstream hub, after which a USB Bus Reset is expected."
Mandatory use EEPROM?
Show LessThe WICED Sense Kit 2 Factory Firmware is the firmware loaded onto the Kit at the factory.
We recommend that the developer use this firmware to restore the device to a known state during troubleshooting.
Show LessWICED SENSE 2 Quick Start Guide (BCM20737L)
Changes from original WICED Sense:
- Leverage BCM20737L with external DC-DC for lower power
- Onboard sensor part number changes for lower power
- Add extra pin-hole in casing for reset/erase capability
We are wishing to baseline one of our products and would ask if you are able to confirm the die revision of your part number S29GL01GS11FAIV10.
Thank you and Regards
Show LessHello,
I have a problem interfacing the CYUSB3ACC-005 FMC from the Xilinx VC707 board.
The DQ0 pin seems to be assigned to FMC pin FMC2_HPC_GBTCLK0_M2C_P that is
not accessible as output from the VC707 board.
This is very disappointing, when I purchased the board I was sure it will work with
any Xilinx FMC based developed board.
Thanks,
Michael.
Show LessHello Everyone,
Something broke down in my PSoC Creator, Pressing Datasheet button in Component menu (see attachment) does not open datasheet. The point is this option worked fine before, I'm not sure what happened. I tried to use PSoC Update Manager to repair "Cypress Document Manager" but it doesn't help. Are there any options to enable this option, without reinstalling the PSoC Creator IDE?
Thank You
Hello everybody
We've faced with very strange issue and need your help to investigate it
We have EZ-USB fx2 (QFN 56-pin) working in slave FIFO autoin mode.
Master device sends serial data (one bit per cycle) on about 19 MHz.
Connection made via pins IFCLK, PB0, PKTEND. Pins SLRD is always active, SLOE pins is always 0 (endpoint 2 is active). PB1-PB7 pins are tied to ground.
Cypress fx2 configured to autoin mode. Here is the code of TD_Init()
void TD_Init(void) // Called once at startup { // set the CPU clock to 48MHz CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1); // slave FIFO mode, IFCLK pin driven by MN88436(SCK pin) SYNCDELAY; IFCONFIG = 0x03; // rev SYNCDELAY; REVCTL = 0x03; // set EP2 direction - IN, TYPE - bulk, BUFFER - 512 bytes, BUFFERING - 4x // FIFOADDR[1:0] = 00 - hardcoded EP2 SYNCDELAY; EP2CFG = 0xE0; // 512 buf4 SYNCDELAY; EP4CFG = 0x0; SYNCDELAY; EP6CFG = 0x0; SYNCDELAY; EP8CFG = 0x0; // EP FIFO RESET SEQUENCE SYNCDELAY; FIFORESET = 0x80; SYNCDELAY; FIFORESET = 0x82; SYNCDELAY; FIFORESET = 0x84; SYNCDELAY; FIFORESET = 0x86; SYNCDELAY; FIFORESET = 0x88; SYNCDELAY; FIFORESET = 0x00; // EP fifo config; SYNCDELAY; EP2FIFOCFG = 0x08; // Autoin, NO zerolen packets, byte-wide //slave fifo pin polarities SYNCDELAY; FIFOPINPOLAR = 0x08; // SLRD - active high, others - active low; // FLAGA and FLAGB configurations SYNCDELAY; PINFLAGSAB = 0x4C; // {FLAGB, FLAGA} - {EP2 PF (blue), EP2 FF (green)} // EZ-USB automatically commits data in this length at AUTOIN mode SYNCDELAY; EP2AUTOINLENH = 0x02; SYNCDELAY; EP2AUTOINLENL = 0x00; //EP2 Programmable flag configuration //[7] DECIS = 1 - PF = 1 when packet >= byte count ) //[6] PKTSTAT = 1 - PF based on byte count alone ) //[5:3] PKTS = Number of commited packets(IN) when PKTSTAT = 0 SYNCDELAY; EP2FIFOPFH = 0xC1; SYNCDELAY; EP2FIFOPFL = 0x00; } void TD_Poll(void) // Called repeatedly while the device is idle { //!Nothing for EP2! EZ-USB doing all the work of transferring packets //from external master(MNMN88436) to EP buffer } BOOL TD_Suspend(void) // Called before the device goes into suspend mode { return(TRUE); } BOOL TD_Resume(void) // Called after the device resumes { return(TRUE); }
Firmware is loading using fxload command
fxload -D /dev/bus/usb/002/002 -t fx2 -I bulksrc.hex
Master device always being started before loading firmware.
Host program (built on libusb-1.0) reads bulk data from cypress fast enough.
!!! The issue is that after 45 minutes of normal working, cypress hangs !!!
Host program reports TIMEOUT error while endpoint's FIFO full flag is set (we have LED signalling on it)
All signals from master (data, clock, packetend) are OK.
Reloading firmware doesn't help, restarting host app doesn't help, system reboot doesn't help.
The only way to make it work again - is to switch power off/on and reload the firmware.
45 minutes interval is pretty stable.
After hang, cypress still can perform control transfers (via EP0), but bulk transfers are broken,
and only hard reset can bring them up again.
What can be a reason of such behaviour?
Any tips are highly appreciated
Show LessHello,
I'm working on a quick design using the CY7C65634 as a 2 port USB hub. There is no EEPROM ( POR configuration is hardwired with pull up or pull down), the main power of the chip is obtained through a external buck regulator (using the usb 5V power supply to output 3V3). There are power management on both ports with a TPS2061 chip. The 2 ports are quite similar ( one is removable, the other is not, and nearly no routing difference)
Whatever the configuration is, I am unable to access the device connected to the second port. I tried with a USB key, an USB audio device and a USB to UART converter. All three are working correctly if directly connected to a USB port on a PC runing window 7 or connected to the first port of the same chip. Nothing happen with USB key or audio device, and windows told me the USB peripheral is not working correctly with the UART adapter.
I have attached a part of the schematics for you to check
Do not hesitate to ask for more information if needed.
Any help would be gladly appreciated !
Show LessWe have troubles with CYUSB3KIT-003 board on some versions of motherboard chipsets.
Evaluation board is used as a transmitter of data from two paralel 16-bit analog-to-digital converters with external 10 MHz clocking. The source codes are attached to the controller. The program is compiled using the FX SDK 1.3.3. The controller works in dual stream bulk mode.
We test our system on different PC with "Streamer" program.
It works on PCs:
1. Desktop PC on CPU i7-3930K with intel X79 chipset with the host controller USB3.0 AS Media XCHI (OS WIN7 x64 SP 1);
2. Laptop ASUS N73JF, chipset B400, host controller FrescoLogic xHCI (OS WIN7 x64 SP 1).
It doesn't work on PCs:
1. Laptop ASUS X550LN with Intel 8 series chipset with extensible host controller Intel (R) USB3.0 0100 (OS WIN8.1 x64 SP 1);
2. Laptop ASUS S400CA with IHM 76 (intel 7 series) chipset with extensible host controller Intel (R) USB3.0 0100 (OS WIN8.1 x64 SP 1);
3. Laptop ACER aspire S3 with intel 7 series chipset with extensible host controller Intel (R) USB3.0 0100 (OS WIN8.1 SP1);
4. Desktop PC on CPU i5-3330 with C261 intel chipset with extensible host controller Intel (R) USB3.0 0100 (OS WIN7 x64 SP 1);
5. Lenovo G580 with IHM 76 (intel 7 series) chipset with extensible host controller Intel (R) USB3.0 (OS WIN7 x32 SP 1);
"Doesn't work" means that if we give 10MHz signal on PCLK pin of the CYUSB board we have only error packets. But if we increase PCLK frequency to 75 MHz we have speed about 290 MB/s. It means that part of packets are lost (about 3% of total). We try different verisons of chipset and USB controller drivers - it doesn't help. Also we try to update BIOS version and it doesn't help too.
How can we see - our software don't works on USB3.0 controler builded in chipset (extensible host controller Intel (R) USB3.0 0100) and prefectly works on PCs where USB3.0 controller is independent from chipset.Other usb devices such as external HDD and USB Flashs, that use USB3.0 port work on Super Speed node on all testing devices.
Can you advice anything to achieve normal work of our program on PCs from the second (don't work) group.
Show LessHi,
Does someone know what is the meaning of PIB error: CYU3P_PIB_ERR_THR0_ADAP_OVERRUN. Only note I found about it is from the source code (cyu3pib.h):
DMA controller overrun on a write to one of the Thread 0 sockets. This typically happens if the DMA controller cannot keep up with the incoming data rate.
It is different than the more common error: CYU3P_PIB_ERR_THR0_WR_OVERRUN, which means writing to a full buffer.
Thread0 in the PIB deals with an auto DMA channel between the host and the GPIF-II. I get this error seldom. Is there anything I can do about it?
Thanks.
Eyal