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Hello!
I encountered a problem when working with CY7C68013.
There are CY7C68013 and FPGA on my board. Data is transferred from the computer to the FPGA and back - all right. But I needed to transmit data from the microcontroller 8051, inside the CY7C68013, to the FPGA. CPU must put the data packet to the endpoint and transfer to the FPGA. Is this possible? Maybe somebody faced with such a task? Can a such a transfer (from cpu to FPGA) carried out without the USB connection to the computer?
Dear,all
We encounter a problem with the USB 3.0 Slave FIFO mode. Any help or input on this is very appreciated.
The periheral equipment is FPGA , we use the internal clock . When the FPGA sends data at the frequency of 50MHz , it works well and the host can receive data successfully . We test the speed is about 190MB/s , but when we change the frequency to 100MHz , the host cant receive any data . I can't find the reason and the solution . Who can help me
By the way,our environment is C#(.NET) , and our chip is CY3014 , the OS is Win7 , 64 bits . We define the producer socket is Socket 0 and the consumer socket is Socket 3, the FPGA write data to address 0.
Thank you.
Kimia
Show LessHi,
I am developing a platform using CYUSB3014 and the 16bit SlaveFIFO interface will be used.
DQ[31:16] are free. I want to use DQ19 (GPIO[36]) as a simple GPIO.
Should I use CyU3PDeviceGpioOverride() to configure DQ19 or just use CyU3PDeviceConfigureIOMatrix() and gpioSimpleEn in CyU3PIoMatrixConfig t?
Thanks.
Show LessWICED™ SMART Software Development Kit
The WICED™ SMART SDK includes the tools and software needed to create BT and networking applications for a wide range of products.
The WICED™ SMART SDK runs on Windows.
The SDK is available as a standalone zipfile or as a separate installer bundled with the WICED™ Integrated Development Environment.
Show LessWICED™ SMART Software Development Kit
The WICED™ SMART SDK includes the tools and software needed to create BT and networking applications for a wide range of products.
The WICED™ SMART SDK runs on Windows.
The SDK is available as a standalone zipfile or as a separate installer bundled with the WICED™ Integrated Development Environment.
Show LessI use the bulkloop between EP0 and EP2(Autoin ,2 buffers) through a vender command,but when I want to read data from EP2,it sometime return random data and total bytes that not the same with the antoinlenhl I have set,somtime it can return the right data ,but when I change the data on EP0 out ,the return data can not change immdiately(the same with the data i have transfered before ). I have reset the fifo in TD_Init why it return random data(why this happen?) ,or the bulkloop can not work on slave fifo mode?Can someone help me? Thanks
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS =0x10;
SYNCDELAY;
// set the slave FIFO interface to 48MHz
IFCONFIG = 0xC3;
SYNCDELAY;
REVCTL = 0x03;
SYNCDELAY;
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
// default: all endpoints have their VALID bit set
// default: TYPE1 = 1 and TYPE0 = 0 --> BULK
// default: EP2 and EP4 DIR bits are 0 (OUT direction)
// default: EP6 and EP8 DIR bits are 1 (IN direction)
// default: EP2, EP4, EP6, and EP8 are double buffered
// we are just using the default values, yes this is not necessary...
EP1OUTCFG &= 0x7F; //set invalid
EP1INCFG &= 0x7F;
SYNCDELAY; // see TRM section 15.14
EP2CFG = 0xE2; //set EP2 valid, in, bulk, 512, double buffer.
SYNCDELAY;
EP4CFG &= 0x7F; //set invalid.
SYNCDELAY;
//EP6CFG = 0xE2;
// SYNCDELAY;
EP8CFG &= 0x7F; //set invalid.
SYNCDELAY;
FIFORESET = 0x80; // reset all FIFOs
SYNCDELAY;
//FIFORESET = 0x82;
// SYNCDELAY;
// FIFORESET = 0x84;
// SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
// FIFORESET = 0x04;
// SYNCDELAY;
// FIFORESET = 0x06;
// SYNCDELAY;
//FIFORESET = 0x06;
//SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP2FIFOCFG = 0x0D;
SYNCDELAY;
EP2AUTOINLENH = 0x00;
SYNCDELAY;
EP2AUTOINLENL = 0x04; //4 bytes in
SYNCDELAY;
// enable dual autopointer feature
AUTOPTRSETUP |= 0x01;
}
BOOL DR_VendorCmnd(void)
{
WORD i;
WORD count;
switch (SETUPDAT[1])
{
//FIFORESET = 0x80; // reset all FIFOs
//SYNCDELAY;
//FIFORESET = 0x82;
// SYNCDELAY;
// FIFORESET = 0x84;
// SYNCDELAY;
// FIFORESET = 0x02;
// SYNCDELAY;
// FIFORESET = 0x06;
// SYNCDELAY;
// FIFORESET = 0x00;
// SYNCDELAY;
case VD_COMMAND:
//FIFORESET = 0x80;
// SYNCDELAY;
// FIFORESET = 0x06;
// SYNCDELAY;
if(!(EP0CS&bmEPBUSY))
{ // check EP0 BUSY bit
if(!(EP2468STAT & bmEP2FULL))
{ // check EP2 FULL(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is full
AUTOPTR1H = MSB( &EP0BUF );
AUTOPTR1L = LSB( &EP0BUF );
AUTOPTRH2 = MSB( &EP2FIFOBUF );
AUTOPTRL2 = LSB( &EP2FIFOBUF );
count = (EP0BCH << 😎 + EP0BCL;
// loop EP0OUT buffer data to EP2IN
for( i = 0x0000; i <count; i++ )
{
// setup to transfer EP0OUT buffer to EP2IN buffer using AUTOPOINTER(s)
EXTAUTODAT2 = EXTAUTODAT1;
}
EP2CH = EP0BCH;
SYNCDELAY;
EP2CL = EP0BCL; // arm EP2IN
SYNCDELAY;
EP0BCL = 0x80;
} // re(arm) EP0OUT
break;
}
default:
return(TRUE);
}
//set the PA.0 as output pin
EP0CS|=bmHSNAK;
return(FALSE);
}
i'm using the cy7c67300 chip and downloaded the firmware to the eeprom,but now i want to erase the eeprom for cycle use it. i know how to erase the eeprom is a very important part of using cy7c67300.so who can help me
thanks
bruce lv
Show LessHello.
I am trying to use the GPIF II Designer and Eclipse in order to design a custom protocol.
I have done a very simple state machine in order to be able to test the basic functions ( CyU3PGpifDisable, CyU3PGpifGetSMState,CyU3PGpifSMSwitch,...).
The State Machine does not behave as expected.
------------------------------------------------------------
I have 4 states:
Start ---(logic1)--> Ready
and
STATE B <---->Ready< ----> STATEA
with all other transitions being logic0 (!logic 1).
Ready toggles FlagA and FlagB. This works fine after starting the state machine -- CyU3PGpifSMStart (START,ALPHA_START)
However, using CyU3PGpifSMSwitch gives unpredictable results.
I execute
apiRetStatus = CyU3PGpifSMControl (CyFalse); CyU3PThreadSleep (50);apiRetStatus = CyU3PGpifSMSwitch(257,STATEB,257,0,10);
to go to STATE B. Reading back the state with CyU3PGpifGetSMState tells me I am at the correct state. PCLK keeps toggling at 100MHz, but none of the state actions are executed (which are just toggling flags. and yes, I have repeat actions until next transactions checked).
----------------------------------------
what is the issue ? I feel like this should be a very easy problem to solve, but I've spent several hours troubleshooting with no luck.
thanks for any feedback. I have attached my code.
Show Less