Product Forum Discussions

 Can't find the soldering peak reflow and also MSL documents for the 1EDN7550U gate driver on the product web page.  There is a good board assembly app note with soldering guidelines, but customer is looking for the peak reflow specification.

Please send, thank you!

Gordy Carlson

Infineon PSS FAE

Is it possible to create an SDIO interface on a PSoC 63 in a WLCSP?
Specifically; is it possible to either split the SDIO to multiple ports or route a UDB based SDIO interface to one of the ports with six or more signals?

There is support for creating a UDB based SDIO interface @ https://github.com/Infineon/udb-sdio-whd
The available library supports an SDIO interface on one of three different ports: P2, P9 or P12. The SDIO interface requires six (6) signals on whichever port is selected for SDIO. Reference the table under "Whats included" @ https://github.com/Infineon/udb-sdio-whd

It appears only a maximum of five (5) signals are available for any of those three ports on a PSoC 63: P2, P9 or P12.
Other ports on the PSoC 63 in a CSP have six or more signals including: P0, P5, P6, P7, P8, P10 and P11.
Reference Table 7 in PSoC 63 CY8C63x6, CY8C63x7 Datasheet @ https://www.infineon.com/dgdl/Infineon-PSoC_6_MCU_PSoC_63_with_BLE_Datasheet_Programmable_System-on-Chip_(PSoC)-DataSheet-v16_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee4efe46c37

Greg

Hello,

We are using a PSoC5LP and just implemented our bootloader. We are going to program the bootloadable application via the i2c bus from another microcontroller.

The other microcontroller is responsible for sending a "Reset" command to the PSOC to get it into bootloader mode.

What is the correct sequence in the PSOC for the bootloadable application to issue a reset command so it can go into the bootloader, and then wait for the specified host link time in the bootloader?

This forum post [Link] says to do the following in the bootloadable application:

    Bootloadable_SET_RUN_TYPE(Bootloadable_SCHEDULE_BTLDR);

    CySoftwareReset();

However, when I browsed the generated source code of Bootloader.c, it appears that if SCHEDULE_BTLDER is set, then it will wait forever for the command, and not even check the wait time set in the bootloader component.

If CySoftwareReset() is used without setting the run type, does the PSOC reset to the bootloadable or bootloader?

We used a PSOC4 in a different application, and our reset process was to enable the watchdog so we could reset from that. PSOC5LP is different, because the watchdog API is not as flexible as the PSOC4. Our watchdog is already going to monitor the application, and the timeout is too much for us to use for this purpose.

Hello.

[1] chapter 8.14.3.1 states "The ECC error detection can be triggered on purpose to test the detection itself and the associated trap routine. This test option is available for RAMs". So, previous stated chapter describes how the RAM ECC error detection can be tested. That’s fine.

My question: How can the flash ECC error detection be tested?
Question reason: In [1] chapter 3.10.7.1 I see the flash ECC description. But I don’t find in [1] a chapter for the flash, which is similar to (above stated) [1] chapter 8.14.3.1.

Regards
Oliver.

References:
[1] https://www.infineon.com/dgdl/xe166h_um_v1.1_2009_04.pdf?fileId=db3a304328c6bd5c01291210b0cb099d

Hi,

I am using XMC4800 controller having 144 pins and 2mb size (XMC 4800 F144x-2048). Previously in my project we use 3 SPIs and now we add another SPI i.e, total 4 SPI we are using and every SPI is in  MASTER and Full Duplex mode and we use SPI_MASTER_0 for communicating with Flash 1 and Flash2 which are same MAKE and it's working fine. Now we add SPI_MASTER_3 and SPI_MASTER_0 is used for Flash1 and SPI_MASTER_3 for Flash2. In the attached image we use different pinouts for different SPIs. SPI_MASTER_0, SPI_MASTER_1 and SPI_MASTER_2 are working properly but SPI_MASTER_3 we are not able to communicate with Flash2.

Is there any issue with this controller by using 4SPI's? 

Best Regards

Anirudh

during build, I got the following in output tab

HDL Generation...
Synthesis...
Tech Mapping...
Error: mpr.M0022: "Net_232" is not a top level pin. Not expecting internal three-state signals. (App=cydsfit)
ADD: mpr.M0037: information: Unused pieces of the design have been optimized out. See the Tech mapping section of the report file for details.
* C:\Users\Larry\Documents\PSoC Creator\LMA Amp Rack APNA Simulation\crosspoint switch test.cydsn\codegentemp\crosspoint switch test.rpt (Tech mapping)
Dependency Generation...
Cleanup...
Error: fit.M0050: The fitter aborted due to errors, please address all errors and rebuild. (App=cydsfit)
--------------- Build Failed: 08/11/2022 10:13:49 ---------------

and the only error in the report file:

Error: mpr.M0022: "Net_232" is not a top level pin. Not expecting internal three-state signals. (App=cydsfit)
Converted constant MacroCell: \SPIM:BSPIM:so_send_reg\ from registered to combinatorial
Converted constant MacroCell: \SPIM:BSPIM:mosi_pre_reg\ from registered to combinatorial
<CYPRESSTAG name="Global Clock Selection" icon="FILE_RPT_TECHM">
Digital Clock 0: Automatic-assigning clock 'SPIM_IntClock'. Fanout=1, Signal=\SPIM:Net_276\
Digital Clock 1: Automatic-assigning clock 'Clock_1'. Fanout=1, Signal=Net_30
</CYPRESSTAG>

questions:
1) what is mpr.M0022 ?
2) how do i find "Net 232" ?
3) what is the actual problem that needs fixing ?

archived files attached

Hello,

I am trying to generate an output frequency of 6 MHz using a PSOC 6 prototyping board but every time I measure the output pin using an oscilloscope its only giving 1.5 KHz. I want to get 6 MHz when I measure the output pin. I have attached the project. Can anyone help please?

Thank you

Overcurrent Protection No hardware shutdown. Software interrupts do not have the highest priority, why?

The optimal solution should be a hardware shutdown.

Hi community ,

                I am using CCg3PA in my project, is there a way to read D+ /D- line status  or voltage from we as source and DUT as sink. Is there a specific function for this requirement.

thanks

Hi,

I followed this link to enable XMC_DEBUG/printf() function.

https://community.infineon.com/t5/DAVE/DAVE-TIP-of-the-day-Semihosting-in-DAVEv4/td-p/309725?p=11700#post11700

However, I got this error at the end. Can you guide me to resolve this? Thank you

<Error content>

"\"C:\\Infineon\\Tools\\DAVE IDE\\4.5.0.202105191637\\eclipse\\ARM-GCC-49\\bin\\make\"" --output-sync -j8 all
arm-none-eabi-gcc: fatal error: c:/infineon/tools/dave ide/4.5.0.202105191637/eclipse/arm-gcc-49/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/nosys.specs: attempt to rename spec 'link_gcc_c_sequence' to already defined spec 'nosys_link_gcc_c_sequence'
'Building target: 1300_LC.elf'
compilation terminated.
'Invoking: ARM-GCC C Linker'
make: *** [1300_LC.elf] Error 1
"C:/Infineon/Tools/DAVE IDE/4.5.0.202105191637/eclipse/ARM-GCC-49/bin/arm-none-eabi-gcc" -T"../linker_script.ld" -nostartfiles -Xlinker --gc-sections -specs=nano.specs -specs=nosys.specs -u _printf_float -u _scanf_float -Wl,-Map,"1300_LC.map" -specs=rdimon.specs -specs=nosys.specs -mcpu=cortex-m0 -mthumb -g -gdwarf-2 -o "1300_LC.elf" "@objects.rsp" -lm
makefile:54: recipe for target '1300_LC.elf' failed