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The EEPROM component in PSoC Creator allows only to write one row (16 bytes) at a time to the EEPROM. There is no provision to write less than 16 bytes to specific EEPROM locations. For partial writes, we can read the complete EEPROM row into a RAM array, modify the desired locations and write the array back to the RAM.
Attached is an example project that shows how to perform a partial write to the EEPROM.
Show LessI think that the instantiation example in the component autor guide (page 43) is false :
cy_psoc3_count7 Counter7Name #(.cy_period(7'b1111111), .cy_route_ld(`FALSE),
.cy_route_en(`FALSE)) (...
I think that the correct syntax is :
cy_psoc3_count7 #(.cy_period(7'b1111111), .cy_route_ld(`FALSE),
.cy_route_en(`FALSE)) Counter7Name (...
Anyway (!!!) my simple 7 bit counter don't works. Can you explain me why ?
Regards
Jean-Louis
//`#start header` -- edit after this line, do not edit this line
// ========================================
//
// Copyright YOUR COMPANY, THE YEAR
// All Rights Reserved
// UNPUBLISHED, LICENSED SOFTWARE.
//
// CONFIDENTIAL AND PROPRIETARY INFORMATION
// WHICH IS THE PROPERTY OF your company.
//
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 05/19/2010 at 10:18
// Component: count7_simple
module count7_simple (
count7,
clk
);
output [6:0] count7;
input clk;
//`#start body` -- edit after this line, do not edit this line
cy_psoc3_count7 #(.cy_period(100),.cy_route_ld(1),.cy_route_en(1))
count7_simple(
/* input */ .clock(clk),
/* input */ .reset(1'b0),
/* input */ .load(1'b0),
/* input */ .enable(1'b1),
/* output [06:00] */ .count(count7),
/* output */ .tc()
);
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
I'm using the EZ-USB for pushing data from my host PC to the device. (Bulk transfers, one way only)
I'm using external logic (Lattice FPGA) that looks only at the Fifo-full interrupt.
I am interfacing the Cypress EZ-USB FX2LP (Cy7C68013A) to a Lattice FPGA. The data is transferred to FPGA through the slave FIFO interface in AUTOIN mode (auto-commit with size of 512-byte) from PC.
Endpoint 2 is used, the fifo uses double buffering with packet size of 512 bytes. The external interface is set to 8 bits wide.
No data handling is performed in the FW code. (TD_Poll is empty)
Problem:
Although I always validate that the overall data length sent from the Host is a multiple of 512 bytes, I guess that under rare conditions an error occurs and a different number of bytes is sent.
This rare condition causes my whole USB channel to come to a stall (I receive Timeouts in my WDU_TransferBulk call) in such a way that only a Hard Reset performed to the chip (pin #99) can resolve.
I am not concerned so much about data being lost in the specific corrupted transfer itself, but more in the ways to recover the channel for further transfers.
A hard reset is not an option, since it requires a redesign of the board, and a hence large delays in delivery.
So I thought to look for some "Soft Reset" that will be equivalent.
I tried two options, in some variants: (but without success) I added code to the ISR_Ures() that performs:
1. Perform FIFORESET to all endpoints. (Copy & Paste from TD_Init)
2. Perform EZUSB_Discon()
Both options brought the chip to some "non responsive" condition. I take it as an option that it is something wrong in my implementation.
I will be more then happy to get your recommendations, since this is a top priority issue in our company, that prevents from tens of machines from being delivered....
---- Please find our original code attached ----
Many thanks,
Shahar.
Hello,
Can someone help with setup of EZMr or some other program for use with Ubuntu Linux. I am trying to change the VID/PID of the device to allow multiple devices to be connected. I looked at the HEXPAD examples, but I'm not very familiar with C.
The device before udev loads the driver is VID/PID 16c0:6000. After loading it is VID/PID 16c0:2972. I really only need to change it by one.
Thanks in advance for any help,
Dan
Show LessHello
Thank you for any help you can provide. Presently we have the FX2 doing a boot loader from a large I2C EEPROM specifically an 24LC512 device from Microchip. That is located at address 1010001(A2=A1=0 and A0=1) as per the TRM. We also have another EEPROM sitting at address 1010101 for extra data store it is also a 24LC512. I would like to combine these two EEPROMs into an 24LC1025 device from Microchip. But this device only allows the setting of A1 and A0 and A2 is not setable. When you access the EEPROM you have to write a value into a Block bit to set whether you read from the upper half of the EEPROM or the lower half. So the address looks something like this 1010BA1A0 where in the setup above A1=0 and A0=1 => 1010B01. Unfortunately I do not think this will work for boot load applications. According to the TRM the FX2 on bootload checks the A2,A1,A0 bits to determine if there is an appropiate I2C EEPROM to boot from. I don't know how this plays with the 24LC1025 situation.
I didn't state above that we wanna boot load out of the EEPROM because we come up USB and enumarate to our own info.
So does anyone know if the FX2 can be setup to use the 24LC1025 or not and how.
Thanks
Gary
Show LessHi,
After installing Creator Beta 4.1 I had problems with aquiring the silicon. The miniprog3 was recognized but not able to connect to the silicon. I had no problems with Creator 4.0.
After some (hot) plugging the miniprog3 didn't enumerate and all leds remain off. I tied several pc's but all the same.
I can't find a reason why the miniprog died, the miniprog was connected to a 5V powered project via the ribbon cable. I only (un)plugged the usb cable several times.
Is there anything I can do to bring back some life in the miniprog. I need it urgent and I only have one dead miniprog (stupid).
Thanks, Rolf
Show LessUsing 68013A 8bit synchronous slave FIFO interface.
EP2 as Hi-speed Bulk IN. FlagA - programmable FULL.
I use FPGA with ChipScope to test FlagA status.
Test: write enable = inactive, continuous clock at IFCLK. I see FlagA toggling. Seems that period proportional to clock period (tested with 33...6 MHz IFCLK). When reading BULK endpoint from CyConsole STALL reported. Reconnecting not help. Asynchronous FIFO interface work (at least no STALLs).
Any comments?
Show LessI'm working with a PSoC 1 evaluation board.
It has only available 2 analog outputs.
More advanced deviced has only 4 analog outputs.
So I think, what matters the analog blocks we have if after all we have a few analog outputs?
Can I use the digital outputs as analog outputs?
Thanks
Show LessI am looking for a board that can act simultaneously as a USB device and as a TCP/IP client over ethernet. I am considering the CY3662. Does anyone know if this board has been used this way before? If so, are there code examples available?
I'm new to Cypress, so I'm not sure how to navigate around and find code/documentation for devices. It looks like resources for the CY3662 are limited. I've looked at the "Getting Started" guide, and its fairly brief.
Show LessGanesh/ Group,
I am using PSoC Express, a MiniProg and a CY3280 Capsense Development kit/card.
I have been having trouble getting the program (*.HEX) into the chip.
I just read your article about the most common solution to this problem.
I don't even think it was my problem, but I tried P1(5) and P1(7) instead of (0) and (1), for Clk and Dta.
Still, "Unable to locate device".
Any other suggestions?
CD