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Hi,

I have a CY8CKIT-143A PSoC4 BLE kit. In the BLE component configuration, I set these two parameters:

Device name: EasyTech N3

Public address: 00A050-000006

So the public address has not been changed from the original one.

The problem happens with CySmart app. If I connect and then disconnect from the device, sometimes in the device list I find severals devices with the same name (EasyTech N3) but different public address. If I try to connect to a device with a wrong public address, I can connect but, of course, services are not recognized.

Have anyone had the same problem?

Thanks for any help.

Andrea

I need to read more than 256 bytes from an I2C peripheral in a single transfer.

The standard component I2CM_0_MasterReadBuf() and associated ISR are limited to 256 bytes due to the cnt variable being uint8 instead of (a more useful) uint16. This is something that does not appear to be configurable at the build level.

I can create a copy of the API function to use locally but is there any way to override the ISR in the build with my own version where I can also change the counter size?

CYBT-343026-01 has an SPI-Flash memory.

Regarding, Erase Endurance and Data Retention specifications of inside SPI-Flash,

I could not find these specifications in module datasheet.

If you have these specifications, please let me know.

I'm looking to send source PDO and sink PDO/RDO info from a CCG2 to an Arduino. I've created a digital output pin in the TopDesign, and am planning to just send the hex value serially.

The hope is to be able to access this info as it's being negotiated. How can I access and send this info?

Thanks.

Looking for a component to create a very simple WiFi based solution.

Problem Description: Monitor if a device is powered on by monitoring its IP address, communicated over the local WiFi network

Possible Solution Scenario:

• When a device power source is "present"/"on", a simple WiFi module will turn on and connect to a predefined WiFi SSID.
• The WiFi module will have an IP address (either pre-set or received via DHCP).
• One can ping WiFi module IP address to conclude if the device is on or off

The WiFi component shall be as simple as posible. No much programming, no commercial monthly fees for wireless < -- > cloud services

I just don't know enough about the product line to find the simplest device that fits the requirements

Thank you in advance

Hello,

We are using a QDR memory (CY7C2665KV18 clocked at 450 MHz with 1.8V core and 1.5V for HSTL logic)  following this datasheet [1] http://www.cypress.com/file/45386/download and these guidelines [1] http://www.cypress.com/file/38596/download.

The QDR memory is connected to a MPF300TS-1FCG1152I/EES FPGA device.  In the current state of our project we have routed all data buses, address and control signals matched in length and impedance (50 Ohm),

but recently, we have noticed that we could have misunderstood impedance configuration following [1] and [2] after having found this forum enough time later [3] https://community.cypress.com/thread/27706?start=0&tstart=0

In [2] at page 11 (Signal integrity and Layout Guidelines), the app note says:

"Cypress Packages are routed to obtain all traces to

50 Ω ± 10%. All traces must be routed to have 50-Ω

impedance and should have no impedance

1. discontinuities."

Ok, done.

"Consider using a series resistor to match total driver

side impedance to 50 Ω."

Ok, this is true if our output driver impedance is less to 50 Ohm, so we decided set the RQ resistor to 250 Ohm. Then at page 24 in [2] 7th paragraph we have:

"The value of the termination resistor (R) is 50 Ω

because most designs have a trace characteristic

impedance of 50 Ω. The termination resistor value

must be equal to the characteristic impedance of the

1. trace."

Considering [3], this is true (close to 50 Ohm) for RQ equal to 175 if Low range setting ODT but output buffers are to 35 Ohm.  Once our tracks are routed this solution is too hard to implement for us at this moment, the same remains for 8th paragraph in [2].

But in the 9th Paragraph of [2], the app says:

"The other recommendation is to keep RQ equals to

250 Ω then the output driver impedance of memory is

50 Ω and with ODT pin low, the ODT value of memory

is 75 Ω. In this case, the reflection co-efficient is

positive with trace impedance of 50 Ω and customer

does not need to use external resistors to match the impedance. "

Can we infer here that the ODT inputs are at 75 Ohm and this does not have remarkable effect in signal integrity? were somewhat confused at these points.

Following figure 39 at page 23 of [2], does this implies that we have to put mandatory termination resistors at WPS/RPS control signals, CP/CP_N, and address bus because there aren't ODT signals?

If we didn't loss anything at this point, we have thought a possible solution to overcome our problem with minimal impact in layout:

Set RQ = 250 Ohm

Set ODT pin Low, so ODT signals at 75 Ohm.

if Address and other ODT signals must be terminated with a pull up resistor (50 Ohm) to VTT, use a VTT termination regulator (for example NCP51400 http://www.onsemi.com/pub/Collateral/NCP51400-D.PDF or another one), and then place 0201 50 Ohm resistors close to Fanout vias.

can be this solution effective? otherwise what are the alternatives?

Thanks in advance

Hello.

Could you please let us know OS supported by CYUSB3033-BZXC?

Best Regards.

Yutaka Matsubara

Our device dropped frames after extending the long line. So we want to measure The rate of USB3.0 transmission of the 1080p@30fps's YUV image before extending the long line and after extending the long line. Can you offer a real measurement data or measuring method?

Dear Cypress.

I have questions about pin strap setting for BC1.2.

Please confirm and answer below questions.

Q1)

Could you please let us know how to enable BC1.2(SDP, DCP, CDP) by using pin strap?

Q2)

When CDP desabled, does DCP become disable in this time?

Or does DCP become enable?

Q3)

Is there a way to enable DCP only by using pin strap?

Q4)

Is it possible to control all BC1.2 modes(SDP, DCP, CDP) with only pin strap setting?

Q5)

Below is Table 6 of DS.

Two conditions are listed under the condition of strapped ‘0’.

Refer to below table, CDP becomes enabled or disabled at strapped ‘0’.

I could not understand a meaning of below table.

What should I think about CDP pin strap setting?

Best Regards.

Yutaka Matsubara

What state of fx3-gpio pin, during power up before firmware upload?

Thanks!

你好，之前有在my case 問過這個問題，貴司fae是回覆要再確認，後來就沒消息了。

想再問，是否已經幫我確認這個問題了。

當FX3一上電後，直到我們的firmware進入成功控制住fx3前，這一段時間gpio的狀態。

請協助確認，感謝！~