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Hi,
I've writen an data acquisition software based on CyAPI wich communicate with an FX2 chip. It use asynchronous bulk communication ( packet size: 512 byte, 16 MByte/sec ). The implementation follow the recommendations of Cypress which can be found in the example programs: overlaped I/O, BeginDataXfer, WaitForXfer, FinishDataXfer.
It works correctly on my previous computer (desktop PC, Windows 7, USB 2.0, i5) but on my new one (Laptop, Windows 10, USB 3.0, 8th gen. i5 ) the transfer always breaks after few seconds.
Could you give me any advice?
Viktor
Show LessHi can someone form Cypress update this last year info?
Thanks
Correct Answer by pmad on Mar 15, 2017 4:50 PM
Thanks for your interest in PSoC 6 and your suggestions for PSoC 6 Prototyping Kit.
1. Yes, we do have plans to bring out a prototyping kit, similar to CY8CKIT-059, but it's not planned till later part of this year. Regarding the CapSense breakout boards, do you have any preference on what kind of sensors you prefer on the board?
2. Yes, we are evaluating the support of C++ in our development platform. We'll announce when we have more details to be shared on this topic.
Thanks,
Pushek
Show LessHi,our customer is thinking use WIFI AD-HOC to connect devices.
So does SDK can support AD-HOC in chip CYW43362,CYW43340 or CYW43438?
If supported,is there any demo?
Show LessHello,
I have the following setup
CYW43907
------------------- (CYW43907)
WICED BR/EDR/LE host stack
HCI over UART
-------------------
.
. UART
.
------------------- (BLE HCI chip)
HCI over UART
BLE Controller
-------------------
Question:
1. My understanding is the WICED BR/EDR/LE host stack must be configured BLE-only host stack to be compatible with BLE HCI chip. How to configure WICED host stack to be BLE-only stack?
2. HCI UART driver is already available in WICED?
3. Do you have any integration guide document?
Best regards,
Xiaodong Xu
Show LessWe are trying to readout the fabrication year of the PSoC from the FLSHID_CUST_TABLES_FAB_YR register. As explained on page 1724 the year is found in the upper 4 bits of the register and contains values from 0 to 9.
What is the significance of those numbers? How do we get the actual year in which the PSoC was produced?
Best regards,
David
Show LessI am using the PSoC4 BLE and sending a notification to the peer when my device shuts down, with a reason code so that the peer knows why my device was turned off (e.g. user action, inactivity timeout, battery low and so on). Obviously on shutdown after CyBle_GattsNotification() I need to loop on CyBle_ProcessEvents(), but I also want to avoid looping too long unnecessarily.
So is there a way to know if / when my notification was put on air? This is an indication so I don't care if the peer doesn't / cannot process it, so there is no need to e.g. use indication and wait for the peer to confirm. All I want to know is if my message was sent, irrespective if the peer got it or not.
Thx,
Karoly
Show LessI need to use i2s and i2c interface in this board.but according to the "CYW920706WCDEVAL Evaluation Kit Hardware User Guide" i2s need to use pin A8 C7 B7 C8.so I2C should use pin E8 D8,but E8 D8 are used to connected to the serial flash.I want to know how to use I2S and I2C in the same time or it is impossible.
Show LessI'm trying to make the OTA update from a CYBLE-202007-01 with a CY5677 BLE Dongle, but the Dongle doesn't recognize the CYBLE-202007-01 when it's advertising in Update mode.
I've followed the instructions for the AN97060 - PSoC® 4 BLE and PRoC™ BLE – Over-the-Air (OTA) Device Firmware Upgrade (DFU) Guide for Upgradable Stack OTA Bootloader using the following Hardware and Software:
- CYBLE-202007-01
- CY5677 CYSMART BLE 4.2 USB Dongle (FW version: 1.2.2.32, HW version 2.0.0.0)
- PSoC Creator 4.1
- CySmart 1.3 (computer with Windows 10)
I've managed to place the CYBLE-202007-01 in OTA mode for receiving a firmware update, and I'm able to successfully update the firmware but ONLY when using the CySmart App with smartphones (iOS and Android) with BLE 5.0 (not working with Android smartphones with 4.1 or 4.2 BLE).
I would like to know if the OTA update of a CYBLE-202007-01 is possible with the CY5677? Is it a Hardware compatibility problem?
I've followed the instructions from OTA update using CYBLE-202007-EVAL not working but this hasn't solved the problem.
I've successfully made OTA updates of an CYBLE-214009-00 with the CY5677 and the Computer CySmart 1.3 without a problem.
Attached you can find the:
BLE_OTA_Stack
BLE_OTA_Launcher
BLE_OTA_Keyboard
Show LessHi Team,
Could you help indicates how to fix the BR/EDR pairing always failed issue after unpair operation was done before?
Detail of this issue is described below.
Environments:
IDE: WICED Studio 6.1.0.85
HW: Android Phone
HW: CYW20719-B1 module
Steps to reproduce:
1. Build and download the app/snip/bt/a2dp_sink project to the CYW20719-B1 module device, and wait the a2dp_sink app started up.
2. In Android Phone device, discover and find the a2dp_sink device.
3. Click the a2dp_sink device to pair and established the connection for the firstly time.
4. After pair and connection established successfully. disconnect and un-pair the Android phone with the s2dp_sink device.
5. Turn off the Bluetooth on the Android Phone, then turn it on again.
6. In Android Phone device, discover and find the ad2p_sink device.
7. Click the a2dp_sink device to pair and established the connection for the second time.
8. Here, we found that the the a2dp_sink device cannot be paired and connected anymore.
We could see 30s timeout issue or PIN code miss-matched error when try to re-connect to the device.
Following is the firmware log that captured when the a2dp_sink firmware running with above steps:
A2DP SINK APP START
a2dp_sink_management_callback 0x15
a2dp_sink_management_callback 0x00
a2dp_sink_write_eir 269bb0
EIR :09 77 69 63 65 64 20 61 32 64 70 20 73 69 6e 6b 20 64 75 64 6c 03 03 0b 11 00 e5
a2dp_sink_management_callback 0x14
a2dp_sink_management_callback 0x14
a2dp_sink_management_callback 0x09
a2dp_sink_management_callback 0x08
Pairing Capabilities Request, bda 94 65 2d 90 c1 42
a2dp_sink_management_callback 0x04
a2dp_sink_management_callback 0x0b
Pairing complete 0
a2dp_sink_management_callback 0x12
NVRAM ID:512 written :136 bytes result:0
a2dp_sink_management_callback 0x0c
Encryption Status Event: bd ( 94 65 2d 90 c1 42 ) res 0
a2dp_sink_management_callback 0x09
a2dp_sink_management_callback 0x08
Pairing Capabilities Request, bda 94 65 2d 90 c1 42
a2dp_sink_management_callback 0x0b
Pairing complete 5
Thanks,
Dudley
Show LessHi,
With customized platform using CYPD-3120 I want to have a USB-C Receptacle instead of plug so that both CC lines are tight. Dongle will have cable flip handling logic based on CC line status.
Can you please let me know(comparing to CYPD-3120 DP reference schematic) how to handle VCONN logic with above scenario?, Do I need to tight VCONN to CC lines? or any other recommendation. Please suggest.
Thank you,
Show Less-
TraveoII
UART buadrate Setting
by chandan1995 Jun 19, 2023