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I got a strange communication issue between a master (XMC 4500) and more than one slave (XMC1201 + port expander card which communicates via SPI).
On my board it's possible to plug in 2 different cards on the same SPI-port (every card gets an chip select and the master toggles between them).
When the master communicates with one slave (MCP23S17 -> port expander card), the waveform of the MISO looks like expected (image below).
The problem starts when the master communicates with both cards -> port expander card and an additional XMC1201 in slave mode (SPI003-app was used).
This looks like the slave is pulling up the MISO-line very strong and the MCP23S17 can't pull the line to ground when it gets the /CS. So the master thinks, due to the wrong voltage level, that the slave sends 0xFF instead of 0x00.
I'm not sure what I can do to prevent this behaviour. In a workaround I could configure the MISO-line to tristate when the end-of-message interrupt occures and reconfigure it at the start of the message (not really smart imho). This could prevent data corruption for other cards.
Thanks in advance for any help !
best regards
Sebastian Show Less
Hello,
could you send me the current datasheets for MB90F897SPMCR-GSE1 and MB90F349CASPMC-GS-N2E1?
I can´t these on www.cypress.com
Thanks.
Best regards
Marco
Show LessDear Sirs,
I'm wondering if FRAMs have some kind of memory organization similar to other memories.
Does 16kbit FRAM consist of 8 pages of 256 bytes blocks/pages or 256 times 8-bytes of rows?
Datasheet of FM24CL16B, page 6 of 19, chapter Slave Device Address it says:
"Bits 3-1 are the page select. It specifies the 256-byte block of memory that is targeted for the current operation."
Same document, page 8 of 19, chapter Endurance it says:
"The memory architecture is based on an array of rows and columns. Each read or write access causes an endurance cycle for an entire row. In the FM24C16B, a row is 64
bits wide. Every 8-byte boundary marks the beginning of a new row."
So should we consider that; it's refreshing an 8-bytes of row not a 256-bytes of block each write/read operation?
Asking this because of our safety concerns. Generally we're working with redundant memory page; ex. for settings we allocate two pages of memory -with checksum of course-, while writing first page in case of noise or power-down, second page will be kept uncorrupted so we can recover.
Waiting for your reply.
Message was edited by: Cesim Can Özer Checked Endurance chapter later.
Show LessJust wanted to check if anyone else is seeing this problem.
We have set up a Gateway node connecting 2 CANnets.
Since the HW Gateway has it quirks http://see https://www.infineonforums.com/threads/5360-Problems-with-FIFO-Gateway-on-XMCs-4400-Multican?, we opted for setting up 4 RX FIFOs and let the irq routines do the data shuffling.
This scheme works almost OK, but we are experiencing MSGLST from a MO in the RXFIFO even though the FIFO is not full.
The CAN_RXOF irq is enabled (and tested OK), but is not asserted in these MSGLST cases.
Fault rate is about 1-2 messages in about 40 millions, so the FIFOs wrapps around numerous times. We also have a FIFO highwater-mark monitor, and it shows that the FIFO is filled with max 2 unread messages at the time MSGLST is set.
FIFO sizes vary from 8 to 20 MOs.
Have also implemented a test command where the RX irq routine can skip n readouts, hence filling the FIFO, and that also works fine. Next irq that reads, empties the FIFO.
We are using the MSIMASK/MSID HW registers to find out which FIFO to read from.
In all the multiCAN examples we have come across, there is no examples on how to empty multiple RXFIFO using the MSIMASK/MSID HW registers.
Hoping someone can chime in on this one.
Here is our irq routine:
bool receive(CanMessage* msg)
{
uint32_t pendingIndex;
int i;
// printf("%s:\n", m_owner);
// printf("MSPND: %08x %08x\n", CAN->MSPND[1], CAN->MSPND[0]);
// printf("MSIMASK: %08x %08x\n", m_msimask[1], m_msimask[0]);
if (m_irqOwner != (uint32_t)(PPB->ICSR & PPB_ICSR_VECTACTIVE_Msk) - 16) {
Can *can = Can::getInstance();
can->s_wrongIRQ++;
return false;
}
for (i=0; i<2; i++) {
CAN->MSIMASK = m_msimask;
pendingIndex = CAN->MSID;
// printf("%-15s[%d] %d\n", "pendingIndex", i, pendingIndex);
if (pendingIndex == CAN_MSI_NO_PENDING) {
if (i == 1) {
return false;
}
else {
continue;
}
}
CLR_BIT(CAN->MSPND, pendingIndex);
pendingIndex += 32*i;
break;
}
// printf("%-15s %d\n", "pendingIndex", pendingIndex);
uint8_t baseIndex = m_messageObjects.front().getNumber();
XMC_CAN_MO_t* baseMoPtr = m_messageObjects.front().getMoPtr();
XMC_CAN_FIFO_SetSELMO(baseMoPtr, pendingIndex);
//printf("%-15s %d\n", "baseIndex", baseIndex);
return m_messageObjects[pendingIndex - baseIndex].receive(msg);
}
bool receive(CanMessage* msg)
{
uint32_t mo_message_lost = (uint32_t)((m_xmcCanMo.can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_MSGLST_Msk) >> CAN_MO_MOSTAT_MSGLST_Pos;
checkAgain:
m_xmcCanMo.can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESNEWDAT_Msk | CAN_MO_MOCTR_RESRXPND_Msk; // reset NEWDAT & RXPND
if ((((m_xmcCanMo.can_mo_ptr->MOAR) & CAN_MO_MOAR_IDE_Msk) >> CAN_MO_MOAR_IDE_Pos) == 1U) { // 29-bit ID
uint32_t identifier = (m_xmcCanMo.can_mo_ptr->MOAR & CAN_MO_MOAR_ID_Msk);
newCanMessage(msg, identifier & 0x000000ff);
msg->size = (uint8_t)((uint32_t)((m_xmcCanMo.can_mo_ptr->MOFCR) & CAN_MO_MOFCR_DLC_Msk) >> CAN_MO_MOFCR_DLC_Pos);
msg->identifier = identifier;
msg->nodeNum = (identifier & 0x0000ff00) >> 8;
uint32_t* dataPtr = reinterpret_cast(msg->data);
if (msg->size > 0) {
dataPtr[0] = m_xmcCanMo.can_mo_ptr->MODATAL;
}
if (msg->size > 4) {
dataPtr[1] = m_xmcCanMo.can_mo_ptr->MODATAH;
}
}
uint32_t mo_new_data_available = (uint32_t)((m_xmcCanMo.can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_NEWDAT_Msk) >> CAN_MO_MOSTAT_NEWDAT_Pos;
uint32_t mo_recepcion_ongoing = (uint32_t)((m_xmcCanMo.can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos;
if ((mo_new_data_available) || (mo_recepcion_ongoing)) {
Can::s_checkedAgain++;
goto checkAgain;
}
if (mo_message_lost) {
m_xmcCanMo.can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESMSGLST_Msk; // reset lost bit
if (Can::s_gatewayEnabled) {
if ((m_number>=CAN_RX12_MOSTART) && (m_number<=CAN_RX12_MOEND)) {
Can::s_lostCntr1++;
} else {
if ((m_number>=CAN_RX2_MOSTART) && (m_number<=CAN_RX2_MOEND)) {
Can::s_lostCntr2++;
}
}
} else {
if ((m_number>=CAN_RX_MOSTART) && (m_number<=CAN_RX_MOEND)) {
Can::s_lostCntr1++;
}
}
// panic_printf(PANIC_USER, "CAN MSG LOST, MO%02d, idle %d%%", m_number, getIdlePercent());
//// panic_printf(PANIC_USER, "LOST MO%02d %08x %08x", m_number, CAN->MSPND[1], CAN->MSPND[0]);
//// printf("\n\nLOST MO%02d %08x %08x\n\n", m_number, CAN->MSPND[1], CAN->MSPND[0]);
// return false;
}
// if (mo_recepcion_ongoing) {
// panic_printf(PANIC_USER, "CAN MSG RX BUSY, MO%02d", m_number);
// }
return true;
}
(Also opened a support case: Case:3740999) Show Less
Hello
We are trying to connect Adesto AT25SF641-MHB-T which is not supported by Wiced.
We can send JEDEC ID (9Fh) command and sometimes get the response from flash memory.
Since It isn't stable, we want to try to change the access timing.
How can we change the timing like SCK clock speed ?
Regards
Show LessCapSense(CSD[自己]+CSX[相互])シングルIDACモードを使用予定です。
(別途IDAC使用予定。"Enable compensation IDAC"をOFFにしております。)
シングルIDACモード時のCSXの動作での影響はどのようなものがありますか?
まだ、シングルIDACモードでもCSXは動作するのでしょうか?
デザインガイドを見る限り、CSXはIDACが2つ必要に見えます。
Show Less
Hi everyone,
I am trying to power up the CY8CKIT-042 (PSoC 4 kit) with a 9V battery using Vin, I have regulated the battery power to 5V, but
the board is not getting powered up.
Can anyone help me with this?
Awaiting response.
Thank You
Arshiya Tabassum
Show LessWe are using the Fx3 with CyUsb3.sys for a new product debvelopment, so far so good.
The driver file CyUsb3.sys carries the version 1.2.3.10.
When retrieving the driver version via CyApi GetDriverVer (this in turn does a IOCTL_ADAPT_GET_DRIVER_VERSION)
we get the version code 0x01020200.
Can someone explain how these two version numbers relate and what they mean in typical version code terms such as Major/Minor/Buld..?
The documantation an the Web do not provide answers.
Thanks,
Michael Wahl
Show LessI am currently working on developing a USB-C based adapter to USB2 that can charge a mobile phone as well as provide USB2 communication. The goal is to be able to connect a USB keyboard to a mobile phone (smart phone) and be able to charge the phone at the same time.
I have worked out the firmware for the most part using CYPD 2122-24LXQIT found in the CY4521 EZ-PD™ CCG2 Evaluation Kit to always do a DR_SWAP to ensure the data direction is correct, and do a PD_SWAP based on a GPIO pin. I have been using this evaluation kit, but, as known, it is not tailored to this specific task. I must provide power to the USB device among other small things.
I am considering the CCG3 because of the fast PD_SWAP feature available and would prefer a completed hardware design platform to soon begin software development.
The following reference design is very close to what I would like to produce for a final solution, and would like ti purchase it from Cypress if there is any stock of the kit available. It is difficult to make and parts are difficult to source in small quantity.
EZ-PD™ CCG3 USB Type-C Charge-Through Dongle
http://www.cypress.com/documentation/reference-designs/ez-pd-ccg3-usb-type-c-charge-through-dongle
Has this PCB been made assembled internally? If there is any stock available it would immensely help with some design.
Can an engineer or sales representative confirm if there is any stock possibly available for purchase of this reference design? I am looking to acquire 2-5 PCBs. I would honestly prefer purchasing a confirmed working hardware platform versus having the PCB fabricated in such small quantity.
Show Less-
TraveoII
UART buadrate Setting
by chandan1995 Jun 19, 2023