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Hi,
I am a newbie to use the FX3 series USB controller.
I am now designing a product using the FX3s to communicate with PC and another special USB host device, which has a strict power limitation below 50 mA.
While attached to the special USB host, the speed is not important.
So I am now looking for every possible way from hardware design to firmware implementation to reduce the power consumption.
Would force the FX3 enter USB 2.0 high speed mode help to reduce the power consumption?
Would the crystal frequency selection between 19.2, 26, 38.4, and 52 MHz also affect the power consumption?
Any other suggestions are more than welcomed.
Thanks,
Jay
Show LessThe problem is that I can't find the handler (is that NMI_handler?) when brown-out detected.
Show Less
//Enable power monitoring control register for brown-out detection.
XMC_SCU_POWER_EnableMonitor(0x01, 0x80);
//enable a trap source
XMC_SCU_TRAP_Enable(0X20);
I do not have a pulse at the WaveDAC8 outputs wc1 or wc2 after the value table is done. I reduced the problem to the Project ‘2_WaveDAC8_TwoWaves’ from the example workspace AN69133. In this example, I measure a static sine as configured in waveform 1 at the output. I also routed signal wc1 to a pin to observe with an oscilloscope, there is no pulse.
My system :
CY8CKIT-059 (CY8C5888LTI-LP097)
PSoC Creator 4.2 (4.2.0.641)
OS Version: Windows 10 (Microsoft Windows NT 10.0.16299.0)
Show LessAs students of the University of Hasselt in Belgium, we are making a master thesis about Power Line Communication on low voltage DC (maximum 48V). Therefore, we are interested in the CY3275 Programmable Low Voltage Powerline Communication Development Kit. We would like to inform us about the availability and price. If this kit is not longer available, do you suggest any other options for us to use?
Show LessHi
We plan to have a double reflow on our board (with a CX3).
Reflow profile is given in datasheet, but it is not written if the component can stand multiple reflow.
Is there any known issue ?
Thank you !
Best regards,
Benjamin
Show LessI had use Cypress USB Serial CY7C65213 demo board as com port in bluetool software.
But it can not successful to get reset command complete log, but logic analysis UART log can show the rest command has complete.
Does Cypress/Broadcom bluetool software only support FTDI UART bridge?
Thanks,
Mitchell
Show LessDear all:
I am facing an issue of CX3 for a long time and wish someone could help me to solve it.
I am using the CX3 to bridge an image sensor to PC with USB3.0 but find that the received framerate is only half of that the sensor transmitted. For example, the sensor's
framerate is 30fps but the PC only gets 15fps.
I happen to find a post saying that the minimum vertical blanking period between two consecutive frames should be at least 200us for CX3. However, I could not find such content in the datasheet. Can anyone confirm this to me?
I also attached a waveform captured from the Oscilloscope. The yellow one is the signal from the data lane. In the middle, there are two short low pulse, where the first one is the EOF of the last frame and the second is the SOF of the next frame. The vertical blanking is only 10us in this case.
Unfortunately, the longest vertical blanking is only 100us for this sensor. So if the 200us vertical blanking is mandatory by CX3, I wonder any other means could be adopted to avoid the loss the framerate in this case?
Really appreciate any help.
Show Less
void
UART_lStartTransmitPolling(
uint8_t * data_ptr,
uint32_t count) {
/* flush FIFO contents */
XMC_UART0_CH0->TRBSCR = USIC_CH_TRBSCR_FLUSHTB_Msk;
do {
/* wait for TX FIFO to become partially empty */
while (XMC_UART0_CH0->TRBSR & (1<}
/* put next byte into FIFO */
XMC_UART0_CH0->IN[0] = *data_ptr++;
} while (--count);
/* wait for FIFO to become empty (= wait for full data sent) */
while (!(XMC_UART0_CH0->TRBSR & USIC_CH_TRBSR_TEMPTY_Msk)) {
}
}
The 1st (FIFO flush) and the last (FIFO empty wait) code lines nullify the optimization of a FIFO. Why would you actively wait until the FIFO has transfered all of its data? And if you do so, why would you flush FIFO contents before the next transfer starts, because there cannot be any data in FIFO on start of the method UART_lStartTransmitPolling(). Using it that way, it makes no difference whether to use the FIFO or not. Better:
void
UART_lStartTransmitPolling(
uint8_t * data_ptr,
uint32_t count) {
do {
/* wait for TX FIFO to become partially empty */
while (XMC_UART0_CH0->TRBSR & (1<}
/* put next byte into FIFO */
XMC_UART0_CH0->IN[0] = *data_ptr++;
} while (--count);
}
Best regards,
Ernie T. Show Less
Idea is to create UT environment in Linux machine and there we can also plugin the code coverage tool etc. which is otherwise not possible in the target (ARM based). Please suggest your view on this ?
Show Less-
TraveoII
UART buadrate Setting
by chandan1995 Jun 19, 2023