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Featured Discussions
I am unable to get smoth operation of toggling led using self capacitance CapSense button
Hello there
I designed an 8bit master state machine with GPIF design tool. I want to control the state machine to send data to the outside. This data may be a fixed data or a changing data. Now I have some problems.
1 How should I set the DMA channel? P2U? P2S? or others, I have seen some examples, but none of them seem to meet my needs
2 How can I generate data and send it out? Are there related API functions?
Here is a screenshot of the state machine I designed
Can you give me some suggestions, I look forward to your reply
Show LessHello.
Tool: Modus 2.2
Target: CYW920719B2Q40EVB-01
How can I configure PUART flow control(RTS/CTS)?
Following is not working properly.
...
[My code]
wiced_hal_puart_flow_on();
wiced_hal_puart_select_uart_pads( WICED_PUART_RXD, WICED_PUART_TXD, WICED_UART_2_CTS, WICED_UART_2_RTS);
...
Show LessHi everyone,
I use CYPD3120.
I get the whole range of voltages from the array, but I can't get 20V.
Could you help me?
Part of the code:
........................................................................................................................................................................................
static ccg_status_t hid_output_data (usb_setup_pkt_t *pkt)
{
uint8_t port;
uint8_t *ptr;
ptr = usb_hid_get_ep0_buffer();
pd_do_t SNK_PDO[5];
SNK_PDO[0].val = 0x0001912C; //5V 3A
SNK_PDO[1].val = 0x0002D12C; //9V 3A
SNK_PDO[2].val = 0x0003C12C; //12 3A
SNK_PDO[3].val = 0x0004B12C; //15V 3A
SNK_PDO[4].val = 0x000640C8; //20V 2A
for(i = 1; i < 64; i++)
{
switch(ptr[1])
{
case PD_5V:
dpm_update_snk_cap(0, 1, SNK_PDO);
dpm_update_snk_cap_mask (0, 0x0F);
dpm_pd_command (0, DPM_CMD_SNK_CAP_CHNG, NULL,NULL);
break;
case PD_9V:
dpm_update_snk_cap(0, 2, SNK_PDO);
dpm_update_snk_cap_mask (0, 0x0F);
dpm_pd_command (0, DPM_CMD_SNK_CAP_CHNG, NULL,NULL);
break;
case PD_12V:
dpm_update_snk_cap(0, 3, SNK_PDO);
dpm_update_snk_cap_mask (0, 0x0F);
dpm_pd_command (0, DPM_CMD_SNK_CAP_CHNG, NULL,NULL);
break;
case PD_15V:
dpm_update_snk_cap(0, 4, SNK_PDO);
dpm_update_snk_cap_mask (0, 0x0F);
dpm_pd_command (0, DPM_CMD_SNK_CAP_CHNG, NULL,NULL);
break;
case PD_20V:
dpm_update_snk_cap(0, 5, SNK_PDO);
dpm_update_snk_cap_mask (0, 0x0F);
dpm_pd_command (0, DPM_CMD_SNK_CAP_CHNG, NULL,NULL);
break;
}
........................................................................................................................................................................................
Show LessI want to create a 0-100uA constant current pulse with 20V compliance for use as biological stimulation device. I was originally planning to use a VDAC and an external voltage-controled current source to generate the current pulse. I then thought about simply using an iDAC and current mirror, but i've never used a current mirror. I think that the
Do you guys think the iDAC + current mirror would be a better choice than the VDAC + current converter?
Show LessHi,
I have a test code running on my custom BSP and it somehow got stuck at cyhal_system_delay_ms(). I ran the debug mode and found that inside cyhal_system.c "cy_rtos_delay_milliseconds(milliseconds);" never returns:
I did include "freertos.h" and "task.h". But even though I don't include these 2 libraries, I still see it got stuck here.
Then I replaced "cyhal_system_delay_ms()" with "CyDelay()" and it works. What is difference between these 2 APIs? And what does it crash at "cyhal_system_delay_ms()"?
Does it have anything to do with the system clock setup?
Thank you!
Show LessI am having an issue with using the emulated eeprom in my project that utilizes BLE on a PSoC6 MCU. I am looking to run the EEPROM on CM0 core only and therefore followed the discussion forums instructions regarding modifying the CM4 linker script. After that I was able to compile the project after adding in the EM_EEPROM object to the schematic. I am now having an issue where the Cy_Em_EEPROM_Write function returns CY_EM_EEPROM_WRITE_FAIL. I am not sure why this may be the case. During debug I can see that the code reaches this function before halting at the handleError function (infinite loop) due to the write_fail return. Perhaps I need to modify the memory location of the EEPROM some how? Any help would be much appreciated. It has already been quite a hurdle to get this far in implementing the eeprom. Perhaps once I get this working we could use it as a new example that is EEPROM with BLE or something like that.
//initial part of my main function on Core0:
int main(void)
{
UART_1_Start();
EEPROM_init();
// Enable global interrupts.
__enable_irq();
..........................................................
}
//EEPROM initialization function
void EEPROM_init()
{
cy_en_em_eeprom_status_t eepromReturnValue;
eepromReturnValue = Em_EEPROM_Init(LOGICAL_EEPROM_START);
if(eepromReturnValue != CY_EM_EEPROM_SUCCESS)
{
HandleError();
}
eepromReturnValue = Cy_Em_EEPROM_Read(LOGICAL_EEPROM_START, eepromArray, LOGICAL_EEPROM_SIZE, &Em_EEPROM_context);
if(eepromReturnValue != CY_EM_EEPROM_SUCCESS)
{
HandleError();
}
/*If first byte of EEPROM isn't 'P' the write data from array*/
if(eepromArray[0] != ASCII_P)
{
/*Write inital data to EEPROM*/
eepromReturnValue = Cy_Em_EEPROM_Write(LOGICAL_EEPROM_START, array, LOGICAL_EEPROM_SIZE, &Em_EEPROM_context);
if(eepromReturnValue != CY_EM_EEPROM_SUCCESS)
{
HandleError();
}
eepromReturnValue = Cy_Em_EEPROM_Read(LOGICAL_EEPROM_START, eepromArray, LOGICAL_EEPROM_SIZE, &Em_EEPROM_context);
if(eepromReturnValue != CY_EM_EEPROM_SUCCESS)
{
HandleError();
}
}
}
Show LessI'm currentely working on aurix TC387, and I want to use Bus MPU to seperate cores.
I created a static configuration on which i specify the START and END address and also the Right.
for exampel :
/* CPU3 DSPR/PSPR regions */
{ (volatile uint32*)&CPU3_SPR_SPROT_RGNLA0, BUSMPU_ALL_MEMORY_START }, /* All SRAM access to CPU3 */
{ (volatile uint32*)&CPU3_SPR_SPROT_RGNUA0, BUSMPU_ALL_MEMORY_END },
{ (volatile uint32*)&CPU3_SPR_SPROT_RGNACCENA0_W, BUSMPU_TAGID_CPU3 },
for the moment I just isolate the core( means that this SPR memory region will be dedicated to CORE3.
My question is if for example I want that this core (core3) contains only CAN1 and LIN1 what shall I do ? Is there any document that explains how can we ensure a peripheral access protection ?
Thank you in advance.
Regards,
Momo Show Less
I'm using a PSoC 5 with the Full Speed USBFS device configured as a CDC in order to simulate a serial port for use with Visual C# and LabView.
The Endpoint maximum packet size is restricted to 64 bytes. Is there a way to increase that and retain the CDC functionality?
Thank you,
Nick
Show Less-
TraveoII
UART buadrate Setting
by chandan1995 Jun 19, 2023