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Hello,

I can see "GPIO Usage Setup in Traveo™ II Family .pdf" for the application note.

I can find the "Selectable CMOS, TTL, and automotive input buffer mode".

But I can not see the value of automotive for .vtrip.

So, I have two questions for CYT2B7.

1. Can all GPIO pins be set to automotive input buffer mode?

2. What is the .vtrip value for automotive input buffer mode?

Best regards,

Yocchi

I need

in RAD HARD Version please

I am looking for S25FL256SDSMFA000 in RAD HARD version

Any suggestions?

Do you have more information on

CYRS1069G30-12GGMB

Thank you

there are two questions.

First, the document AN65974 said:(a) The number of data words available for reading (while keeping SLOE# asserted) after the clock edge at which the partial flag is sampled asserted = watermark x (32/bus width) – 1.But when i run the program which have modified based on the AN65974 routine. I found that SLOE keeping 6 clk，and i am sure that the watermark of flagd is 6.This why? 

Second, I have modified the FM based on AN65974, i only set one endpoint for data from PC to FPGA.  I have modified the verilog code based on AN65974.   When i transfer many Bytes from control center,FPGA work nomally.But when i transfer a few Bytes from control center, there was an error code 997,and Flagd stay on 0. When i use the software designed by myself, the function xferdata will return false.

can you provide some thoughts to locate reason of those 

I am using CYUSB3324 hub. if i disable pin-strapping (not using pin-strapping configuration), only using  ''EEPROM'' for  configuration, so in this case i don't connect pull up and pull down resistor to GPIOs. i only want to use GPIOs for LED. Now in this particular situation these LED GPIOs are active low or active high?