I'm seeking a very-low-parts-count, galvanically-isolated DC/DC converter.
Something like the TLE8386-2EL, but faster, to reduce transformer size.
We need to buck/stepdown.
Must support multiple outputs, ie series transformers. It's important for the outputs to be galvanically isolated from each other.Show Less
I am designing a 325V nominal DC to 72V DC convertor using ICE1HS01G-1. But don't get any solution from the datasheet or demo board documentation. So what is the way for feedback circuit design?
Thank in advance
I'm a bit confused. So I have drawn the gain-curves of the LLC converter. And they look fine on the nominal frequency scale:
In the diagram the numbers in the legend are the amount of load with 1 being 1500W at 100V output load. The formula used are:
Mg = 1/sqrt(Qe**2*(-fn + 1/fn)**2 + (1 + 1/Ln - 1/(Ln*fn**2))**2)
with fn=fsw/fr; Ln=Lm/Lr; Qe=sqrt(Lr/Cr)/Rac; Rac=8*Vout**2*n**2/(pi**2*Pout)
But when i determine the resonant frequencies for different Loads (graphically determined - cross checked with calculation) and draw the gain-curves across the switching frequency the area of the frequency range is way off than the desired 500kHz resonant. It's some where between 169819Hz -298807Hz.
The NullMg represents the gain-curve for the Null Load case.
The MaxiMg represents the gain-curve for the Maximal Load case, which is here the 1500W.
The FullMg represents the gain-curve for the Full Load case.
I was expecting a wider range when plotting the gain-curves with the resonant frequency for each load. Due to the relation between the resonant frequency and the load. But I did not expect such a big deviation.
Is this big deviation normal, or is maybe something with my fundamentals flawed?
Thanks for any advice.
PS: I used Ln=6; Qe=0.4 to determine the resonant circuit.
It should be noted that I know that choosing a smaller Ln results in a narrower frequency range, but additionally it results in increased conduction losses and decreased commutation losses.
Additionally a big Ln results in a big Lm, which is needed to keep the ZVS.
I enable the window watchdog in INIT state and it can move to NORMAL state. Then, when I make an overflow and restart the program to initialize the IC, it stuck/returns/stops in INIT state.
However, when I disable watchdog once, then the IC wouldn't be stuck in INIT state.
I set INITERR = 11111100 to clear the failure flag. And read the status flags from 1A to 1F, there is no error.
If I don't want to disable the watchdog once in INIT, what should I do? Or What mistake did I make?
AN-1138 is described as follows:
1. How is condition 3 calculated, can you give an example? Is Vin an rms or peak-to-peak?
2. Is R1 related to the input voltage? If PWM is determined to be 360khz, how is R1 calculated? What is the effect of the value of R1 on the startup of 2092?
3. The following figure is the parameter I set, is it reasonable? Whether it affects the 2092 self-oscillation。
4, as shown in the figure below, I see that IRADAMP7s and IRADAMP5, IRAUDAMP9 are different in the feedback network, IRAUDAMP7s does not have Rfb1 and CFB, IRAUDAMP5, IRAUDAMP9 there is Rfb1=1k and CFb=150pf, what is the role of this RC for 2092 self-oscillation? IRAUDAMP7s are not required?
Customer has MERUS™ audio amplifier and this is connected to a raspberry zero w and Volumio and is not displayed in the menu under playback.
They used MERUS™ audio amplifier (KIT_40W_AMP_HAT_ZW).
They did everything and read the documentations. However, they can't find the required Volumio image on the Github page. The driver for the MERUS™ Audio Amplifier is not listed under Volumio.Show Less
I have a doubt regarding the IRPS5401 tracking mode.
Looking at the UltraZED carrrier card PS schematic, the LDO output is NOT connected to LDO_FB with resistor divider feedback:
From what is seems, the IRPS5401's LDO is configured in NON tracking mode. This is what I understand also from the device evaluation kit user guide (https://www.infineon.com/dgdl/Infineon-UG-IRSP5401Demoboard-UM-v01_02-EN.pdf?fileId=5546d4625e37f35a015e37f7da400002)
The guide says that:
Sink/Source (Tracking) mode
Set REG 0x1420 bit  (ldo_track_config) to 1
In Tracking mode, VO_LDO must be connected directly to FB_L.
But when I look at the programmed register map from IR PowerIRCenter software (Read All Reg and the Save config file), it results that:
REG 1420h = 72FFh
where the 8th bit is set to 0, which would mean that the LDO is in non-tracking mode.
What am I misunderstanding about this configuration ?
Could someone clarify this ?
我们使用XDPS2201做65WPD，我们购买了IF-BOARD.DP-GEN2,也顺利下载并安装了.dp Vision GUI软件。但是软件启动启动提示：
Recently, I brought two set of eva board, refxdpl821035W & refxdpl8221, and try to communicate with them using dp. gen 2.0 interface. But both of them need to use different dp. version, i.e dpifgen2rev1-12-0 hex for xdpl 8210 & dpifgen2rev2-5*-0 hex for xdpl 8221. Is it correct?
Besides, I always got the error message ' Aparam out of batch' while change the setting of xdpl 8221
Recently I purchased https://www.infineon.com/cms/en/product/power/dc-dc-converters/digital-multiphase-controllers/gang-programmers/prg540101-4a/ PMIC programming Adaptor to program IRPS5401M. I followed user Manual instructions to get access for Setup files. Unfortunately didn't work. Let me know if there is a way to get access to setup files