Power Management ICs Forum Discussions

Hi, in the IR38060 datasheet Rev.3.9(8/18/2016), PVin was changed from 21V to 16V in the spec table.

I am wondering if this revision only correction in the datasheet or change in the actual IC.

Thank you.

In heavy load conditions, TDA38825 experiences an upward trend in voltage

vout setting :0.8V

iout 15A

#TDA38825

#TDA38812

#TDA38806

Firstly, I have let the FO3/TEST pin to GND and in development mode SBC don't produce a reset because the watchdog is not fed.

But When I slowly lowered the power supply from 12V to 0V and then slowly ramped up to 12V, the reset kept happening because the watchdog was not fed, even though FO3 was connected to ground. I don't know why?

From the below pic, the VPOR,r must be earlier than VRT1,r. So no matter how slow the power supply rises, the SBC will always move from OFF mode to INIT mode first. As soon as the SBC enters INIT mode, it will definitely enter development mode because the FO3 pin is connected to ground. 

Hi,

The XDPP1100 provides the method of forced duty cycle T1, T2 for PWM generation. The registers rampX_force_t1 and rampX_force_t2 have an LSB resolution of 5 ns. In the technical reference manual, it is said that "it is possible to provide additional time resolution to both t1 and t2 via rampX_force_duty[5:0] according to Equations (7.8) and (7.9) when t1 and t2 are forced”. You can find it on page 141 in the document.

What's the effective time resolution with this method? How to use this feature and can you elaborate it more in detail?

Is there a Spice model available for this controller, or has anyone had any luck modelling it?

Poweresim is OK, but lacking useful Inductor/Tranformer core models and I've had no luck getting the Web-based TINA thing to work - just keeps throwing licensing errors. As Spice models are available for every other component, it would be really useful to get one for this!