Power Management ICs Forum Discussions
Does TLE4263-2ES require an external pull-up at reset out?
Datasheet says it has an internal pull-up(30kΩ) but in the application circuit there is a 5.6kΩ pull up which is contradicting. (30kΩ parallel 5.6kΩ would reduce the pull-up effective resistance).
Show LessI faced a rudimentary problem with ICE5QSAG. The start-up of the IC is not working. Powering up the IC with external 15V DC source starts up IC. It continues to work after removal of external DC power.
The application details :
1. Application : Lead Acid (7AH SMF) battery charger
2. Flyback Converter
3. CVCC Controller based on SEA05 IC of ST
4. Ourput : 13.5V, 1A (CVCC)
Naresh
#ICE5QSAG
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Could you please teach the failure rate of the VCP function (17pin) of TLE9461ES?
The gate signal of the battery's reverse connection protection FET is driven by this charge pump. If the VCP function is lost, the system may malfunction. Therefore, I would like to know the failure rate of individual parts.
Best Regards,
Tetsuo
Hi all,
I think that the data format of vout_transition_rate and ton_rise is Linear.
The values of vout_transition_rate and ton_rise are as follows.
In decimal format, vout_transition_rate is 1(8×2-3)[V/ms].
In decimal format, ton_rise is 1(2×2-1)[ms].
Are these correct?
Also, please teach me what u7.3 and s-1.7 stand for.
Best regards,
MS
Hi Infineon Team,
we using ICE2HS01G for our Charger,Power rating 1500Watts
Vinput=415V DC(Min 380V, max is 420V DC),switching frequency is 100KHZ,Output voltage is 59V,25A DC, using STM 32 Controller to set current
We adopted circuit from feedback section of 2KW Battery charger Evaluation board
https://www.infineon.com/cms/en/product/evaluation-boards/eval_2kw_48v_char_p7/
we followed design calculation of ICE2Hs01G application notes and made a prototype.
For LLC , Lr and Lm are Integrated magnetics,Lr is leakage inductance
Lm=160uH
Lr= 30 uH
Cr= 300nF
and for feedback path, set value changed to 1.7V since we are using ST controller , 3.3V supply instead of 5V(xmc series of evaluation board ) attached is schematic for your reference.
No load condition ,output voltage set at 62V and in Burst mode .
Problem is at full load 59V,25A (rheostat load)resonant condition is not happening, LLC fet is getting too hot, by changing set value to 2V,we are encounter Missing cycle mode also(still heating and produce noise at transformer),i have no idea about setting this ref voltage at optimum point.
Kindly help me to solve this problem
Thank you
venkatesh B
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TLE9012 UM said that in the ring mode the EMM signal will follow the path that shows the RX interface back to the microcontroller. If the contiguous device shows a TX interface, the message will not be forwarded.
But I had a question, The EMM signals how to communicate if the chain is not in ring mode and TLE9012 is in normal operation. The contiguous device shows a TX interface, the message will not be forwarded? or the contiguous devies will change the Tx, Rx interface?
Thanks
Show LessDear All
Goodnoon
Please help me to understand why the waveform in not continuous:
Yellow: Primary Current, Blue: Output Voltage, Red: HS Vgs, Green: LS Vgs
Regards
Show LessMy customer designed PMICs, IR35215 and IRPS5401 for new Xilinx FPGA Versal according to reference guide and schematics.
But I could not find any configuration files on the web page.(
I want to know whether IFX provide a PMIC configuration file or not, and where I can find them.
Show LessHello everyone
do I need additional boards if I want to use the board with my own battery management system? So, for example, the transceiver board?
Is there anything else special that I need to consider?
Thanks in advance
Show LessThank you for this information. I was very confused as to why an "n.c." pin is pulled out at all, but it seems to be going to ground.
I am having issues with the TLE9015. When I provide power on VS (12-28 V) I am expecting Vreg to go to 3.45 V, VDDC to go to 2.5 V, and nSleep to be pulled to 3.3 V. Instead, all three pins are at 0 V. When I force nSleep high by providing 3.3 V, Vreg goes to 1.24 V, and VDDC remains low. I have VIO directly connected to Vregout.
Can you please state the expected chip behavior when supplied power on the VS pins?
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Power Management ICs
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