Can PCB Cu traces be used as a current sense resistor in XDPP 1100 controller? If yes, then how to calculate trace resistance and what layout guidelines needs to be followed?
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In one of the applications, I am using TLE4476D operating both channels sourcing 100mA. While operating the IC at room temperature IC heats up to 70 degrees Celcius. When I test the IC at 60 degrees Celsius, IC starts to shut down and power on repeatedly, to be specific it shutdown every 2 Sec for the duration of the 500mS to 1S.
The same thing is observed in the TLE4267GM IC testing with the same environmental conditions. The output current is 100mA while testing.
Kindly tell me the reason for this happening. It will be great if you can provide me with a solution for the same.
I am applying 28.5V at the input of the IC.
I understand that to configure WWD, set the 0x06~0x0A register after trigger in LOW.
Although WWD has been implemented in the system, I am inquiring because it sometimes starts with an increase in Err Cnt in the initial drive.
Does changing the value of the WWD register restart the LOW? Or does CWOW continue with the changed value?
I would like to know which state (INIT, NORMAL) and at which point it is advantageous to change the setting of the WWD.
In the currently configured system, the symptoms are as follows.
1. Trigger at LOW (Initial setting 600ms)
2. Set up WWD-related registers in Protection Registers.
3. Trigger accordingly with the thought that the CW & OW changed to the setting value will continue.
If no. 2 is performed only once, the ERR CNT rises to 2 once, and then the correct trigger gradually continues to converge to 0.
If no. 2 is performed several times (less than 10 times at 10 ms TASK), it operates without increasing ERR CNT.
"TOUT temperature output pins of multiple power stages are OR-tied together so that the power stage with the hottest temperature (highest TOUT voltage) will drive the signal line to the controller xTSEN pin."
Why the controller does not read an average value but a highest value with an OR-tied
Could you please list some possible risk when we use a 4.7uF capacitor?Such as when and what kind of problem will it
happen?If problems happened,where would it be affected?Could you provide us with some directions?
And here are some other qusetions——If we connect a 1KΩ resistor in series on SDO and CLK，is the value of resistor too
large?is there some risk for SPI communication?Do you have recommended values or ranges?
Looking forward to your reply!
Is there any spreadsheet for any of the IDP230x?
In the design guide (DG_201702_PL21_007), in Fig. 11 there is a screenshot of something that looks like that (very ambiguous tho~).
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I am having some quries related to "ERR" flag used in SPI Communication in SBC TLE9471ES.
As per manual this flag is set when
1. number of received spi clocks is not 0 or 16
2. RSTN is low and SPI frames being sent at same time
so the queries are
1. What happened if we dont take action when the ERR flag is set
2. Is there any alternative available like SPI_FAIL flag to cover this errors
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I am powering an Intel Arria 10 FPGA and am using your power demo board design as a starting place: https://www.infineon.com/cms/en/product/promopages/Altera/
Is there a recommendation for a different IR MOSFET than the IR3555-IR3557 to use with the IR35204? These FETs are obsolete or unavailable.