I am Rocky and testing the TLF35584 with TC234.
May I ask how to configure the FSP in TC234 so that it can make error monitoring function in TLF35584 enable without error?
According the TLF35584 datasheet, there are many related frequency at p.151 (12.2 Electrical Characteristics). Which frequency is required for setting the FSP?
Valid ERR input signal frequency? Or Invalid ERR input signal detection time (low frequency)?
In addition, according to TC234 datasheet.
Does it mean that the minimum fault state duration is equal or great than 250us?
Thank you for your reading and please give me advice.
Hello,
Thank you for posting on Infineon Community.
Fault-free and fault state behaviour of FSP protocol can be configured with the following protocols:
- Bi-stable protocol (default)
- Time-switching protocol
FAULT Free State
Let’s consider FSP is configured as Time-switching protocol, which means FSP[0] is toggled between logic level 0 and logic level 1 with a defined frequency (TSMU_FFS/TFSP_FFS) is the corresponding time period) in the fault free state as shown below
This frequency is configured via the SMU_FSP register and its value should be within the valid frequency range mentioned in the Electrical characteristics of PMIC TLF35584
Note: Above spec is not applicable for Bi-stable protocol
FAULT State
This frequency modulation protocol is violated when the SMU enters the FAULT state.
When an alarm configured to activate the FSP, the SMU automatically switches to the FAULT state, remains in this state until a SMU_ReleaseFSP()
command is received and TFSP_FS (Minimum duration of FSP Fault State) is satisfied or a Power-on Reset takes place.
Below is a snapshot to calculate TFSP_FS
As the FSP is active for at least TFSP_FS (see SMU_FSP register), it is ensured that the safe state of the system is entered through external mechanisms independent from the microcontroller (besides FSP itself).
Any frequency in the invalid range mentioned below on the ERR pin will be considered invalid by PMIC and will lead to change in the safe state output.
Let’s consider the below diagram to understand more
ERR pin toggles in the fault free state of uC with a frequency (TFSP_FFS in time) set via SMU_FSP register which should be within valid ERR input signal frequency mentioned above.
As soon as uC triggers an alarm and activates SMU_ActivateFSP(), uC enters into fault state for a time period of TFSP_FS (configurable via SMU_FSP register). When TFSP_FFS is violated after a delay of ∆tdet (Invalid input signal detection time), Safe state logic of PMIC activates the safe state outputs.
Please reach out to us if you need further assistance
Regards
Anil
Hello,
Thank you for posting on Infineon Community.
Fault-free and fault state behaviour of FSP protocol can be configured with the following protocols:
- Bi-stable protocol (default)
- Time-switching protocol
FAULT Free State
Let’s consider FSP is configured as Time-switching protocol, which means FSP[0] is toggled between logic level 0 and logic level 1 with a defined frequency (TSMU_FFS/TFSP_FFS) is the corresponding time period) in the fault free state as shown below
This frequency is configured via the SMU_FSP register and its value should be within the valid frequency range mentioned in the Electrical characteristics of PMIC TLF35584
Note: Above spec is not applicable for Bi-stable protocol
FAULT State
This frequency modulation protocol is violated when the SMU enters the FAULT state.
When an alarm configured to activate the FSP, the SMU automatically switches to the FAULT state, remains in this state until a SMU_ReleaseFSP()
command is received and TFSP_FS (Minimum duration of FSP Fault State) is satisfied or a Power-on Reset takes place.
Below is a snapshot to calculate TFSP_FS
As the FSP is active for at least TFSP_FS (see SMU_FSP register), it is ensured that the safe state of the system is entered through external mechanisms independent from the microcontroller (besides FSP itself).
Any frequency in the invalid range mentioned below on the ERR pin will be considered invalid by PMIC and will lead to change in the safe state output.
Let’s consider the below diagram to understand more
ERR pin toggles in the fault free state of uC with a frequency (TFSP_FFS in time) set via SMU_FSP register which should be within valid ERR input signal frequency mentioned above.
As soon as uC triggers an alarm and activates SMU_ActivateFSP(), uC enters into fault state for a time period of TFSP_FS (configurable via SMU_FSP register). When TFSP_FFS is violated after a delay of ∆tdet (Invalid input signal detection time), Safe state logic of PMIC activates the safe state outputs.
Please reach out to us if you need further assistance
Regards
Anil
