TLF35584

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Nachiket_Wawoo
Level 1
Level 1
First solution authored 5 replies posted First reply posted

TLF_2023-05-19_16-54-11_2.jpeg

Hello Experts,
As per attached image, the problem which i am facing is that the QUC 3V3 signal is not rising till 3.3V and also TLF is going in FAILSAFE mode.  
Below image is for PREREG against VS.

TLF_2023-05-19_17-49-44_1.jpeg
TLF is interfaced with microcontroller but its not powered ON as micro power supply is controlled by TLF EVC pin.
Any leads to resolve the issue?

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1 Solution
Albab_A
Moderator
Moderator
Moderator
5 likes given 50 solutions authored 100 replies posted

Hello Nachiket,

We observed many test cases which might lead to failure and device moving to FAILSAFE due to power up sequence like- Slow Vs slew rate and therefore not crossing threshold value which makes Vprereg discharge and leads to failsafe, some Vprereg issue etc. We also notices that MPS pin is also not responsible for failure event neither is the case with defect in specimen itself.

Only thing that is left to check is PCB . As we see that QUC is not able to cross the threshold mark but it does follow the Vprereg there might be some UV detection across QUC which is making the device go to failsafe. There might be a possibility of any short to ground for QUC etc. So carefully check the PCB. If possible send clear image of PCB also please.

Best Regards,

Albab

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15 Replies
Albab_A
Moderator
Moderator
Moderator
5 likes given 50 solutions authored 100 replies posted

Hello Nachiket,

Can you send me the status of MONSF register also. There might be possibility that QUC crosses UV for T,stg period resulting the device to move to failsafe. To further diagnose the issue clearly, can you provide IF MONSF register status if possible.

 

Best Regards,

Albab

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hi,
my microcontroller power supply is supplied by external converter which is controlled by TLF EVC pin which is at present pulled Low. due to this i dont have access to SPI registers of TLF. 
lets assume possibility that QUC crosses UV for T,stg period resulting the device to move to failsafe, what could be causes of that and possible solutions? the QUC is not used in my circuit anywhere at all.
Thank you in advance.

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HERE IS THE waveform with MPS enabled and disabled and ROT signal:

_LAD4xA_TLF_MPS_ROT_2023-05-22_15-15-01_5.jpeg

_LAD4xA_TLF_MPS_ROT_2023-05-22_15-14-46_4.jpeg

  

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Albab_A
Moderator
Moderator
Moderator
5 likes given 50 solutions authored 100 replies posted

Hello,

Did you placed QUC Output capacitors (At least 1uF) for proper startup of power rails? Later you can disable via SPI if you doesn't want to use. 

Best Regards,

Albab

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hi,
yes we have 2x MLCC 3.3uF cap on QUC line.

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Nachiket_Wawoo
Level 1
Level 1
First solution authored 5 replies posted First reply posted

below is the circuit:

Nachiket_Wawoo_0-1684750121094.png

 

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Hi,

As I can see from the waveform that Vc1 is nearly zero volts. If you are using external post regulator, VCI pin should have a valid voltage range, otherwise this is considered as short to ground by PMIC and move to failsafe can happen.

Best Regards,

Albab

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Nachiket_Wawoo
Level 1
Level 1
First solution authored 5 replies posted First reply posted

_LAD4xA_TLF_VCI_2023-05-22_17-19-38_2.jpeg

 i tried to keep VCI to 0.868V from the initial, still no change.

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Nachiket_Wawoo
Level 1
Level 1
First solution authored 5 replies posted First reply posted

_LAD4xA_TLF_ENA5V_2023-05-23_12-16-00_1.jpeg

 one more experiment i tried is to provide ENA after TLF enters in FAILSAFE mode... now TLF tried to wakeup but only for one time as visible in waveform.

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Hello Nachiket,

We have scheduled one meeting with the internal R&D team regarding this failsafe issue. We already worked on different test cases which could lead to failsafe but none of them are satisfying your schematics and waveform. I will update you at the earliest with possible conclusion.

Best Regards,

Albab

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_LAD4xA_I_QUC_2023-05-23_18-07-11_9.jpeg

_LAD4xA_I_QUC_2023-05-23_17-13-16_8.jpeg

_LAD4xA_I_QUC_2023-05-23_17-11-52_7.jpeg

Hello ,

i have also tried to capture the current from QUC. please find attached images.

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Albab_A
Moderator
Moderator
Moderator
5 likes given 50 solutions authored 100 replies posted

Hi,

Understood. Can you please check whether this given failsafe event is limited to this specimen or you have observed in some other pieces of IC as well?

Best Regards,

Albab

 

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Nachiket_Wawoo
Level 1
Level 1
First solution authored 5 replies posted First reply posted

This behaviour is on all the 30 boards which we manufactured.

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Albab_A
Moderator
Moderator
Moderator
5 likes given 50 solutions authored 100 replies posted

Hello Nachiket,

We observed many test cases which might lead to failure and device moving to FAILSAFE due to power up sequence like- Slow Vs slew rate and therefore not crossing threshold value which makes Vprereg discharge and leads to failsafe, some Vprereg issue etc. We also notices that MPS pin is also not responsible for failure event neither is the case with defect in specimen itself.

Only thing that is left to check is PCB . As we see that QUC is not able to cross the threshold mark but it does follow the Vprereg there might be some UV detection across QUC which is making the device go to failsafe. There might be a possibility of any short to ground for QUC etc. So carefully check the PCB. If possible send clear image of PCB also please.

Best Regards,

Albab

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Albab_A
Moderator
Moderator
Moderator
5 likes given 50 solutions authored 100 replies posted

Hello,

I have taken the FAE in sync who created the case at Microsoft Dynamics platform. Will come across a possible solution for sure.

 

Best Regards

Albab

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