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t2355638
Level 1
Level 1
5 sign-ins First reply posted First question asked

After init TLF35584 and go to normal
I Send to SPI CMD get DEVCTRL and DEVSTAT.
TLF35584's STATE is normal but STATEREQ is still normal.
Why STATEREQ is not reset to 000.


read DEVSTAT 27h
78 0
rw addr data p
0 100 111 0 0000 000 0

RX
129 245
rw addr data p
1 000 000 1 1111 010 1 STATE is NORMAL
-----------------------------------------------------------------------
read DEVCTRL 15h
42 1
rw addr data p
0 010 101 0 0000 000 1

RX
129 212
rw addr data p
1 000 000 1 1101 010 0 STATEREQ is NORMAL

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1 Solution
Polimera
Moderator
Moderator
Moderator
10 likes received 100 replies posted 50 solutions authored

Hello t2355638,

Just FYI

129 245
rw    addr              data              p
1    000 000       1 1111 010     1

in RX the  000 000 bits represent the status .. Not the address..

In our GUI we tried to execute the state transition to NORMAL and the PMIC moves to NORMAL. We read back the DEVCTRL & DEVSTAT registers,

DEVCTRL data bits  E8= 1110 1000 which shows that the STATEREQ is RESET

DEVSTAT data bits FA = 1111 1010  means the PMIC is in NORMAL state. 

The Bit-Field STATEREQ in DEVCTRL is type rwhc (readable-writable-hardware-cleared). So assuming a correct state transition request (DEVCTRL + DEVCTRLN), theoretically one could read it back after writing before the request is processed. Nevertheless the time between rising edge of Write command completing the request (DEVCTRLN) and the finalization of the processing is just in the range of ~1µs typically. Some times the STATEREQ bit may not reset due to some delays and other timing issues. Better read DEVSTAT.STATE and check whether the desired state is reached finally.

 

Regards,

Kranthi

 

 

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5 Replies
Polimera
Moderator
Moderator
Moderator
10 likes received 100 replies posted 50 solutions authored

Hello t2355638,

How can you assure that PMIC is in NORMAL state?

 

RX
129 245
rw addr data p
1 000 000 1 1111 010 1 STATE is NORMAL- this address is not related to DEVSTAT bit.

Did you write the DEVCTRL & DEVCTRLN  inverted bitwise?

Have you followed the sequence for the protected registers?

Regards,

Kranthi

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Yes. I write the DEVCTRL & DEVCTRLN.

I send to PMIC for read DEVSTAT(27h)
78 0
rw    addr               data        p
0    100 111      0 0000 000 0

And this is recieve from PMIC.

129 245
rw    addr              data              p
1    000 000       1 1111 010     1

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Polimera
Moderator
Moderator
Moderator
10 likes received 100 replies posted 50 solutions authored

Hello t2355638,

Just FYI

129 245
rw    addr              data              p
1    000 000       1 1111 010     1

in RX the  000 000 bits represent the status .. Not the address..

In our GUI we tried to execute the state transition to NORMAL and the PMIC moves to NORMAL. We read back the DEVCTRL & DEVSTAT registers,

DEVCTRL data bits  E8= 1110 1000 which shows that the STATEREQ is RESET

DEVSTAT data bits FA = 1111 1010  means the PMIC is in NORMAL state. 

The Bit-Field STATEREQ in DEVCTRL is type rwhc (readable-writable-hardware-cleared). So assuming a correct state transition request (DEVCTRL + DEVCTRLN), theoretically one could read it back after writing before the request is processed. Nevertheless the time between rising edge of Write command completing the request (DEVCTRLN) and the finalization of the processing is just in the range of ~1µs typically. Some times the STATEREQ bit may not reset due to some delays and other timing issues. Better read DEVSTAT.STATE and check whether the desired state is reached finally.

 

Regards,

Kranthi

 

 

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Do you have any solutions for the delay and timing issues with the STATEREQ bit? Or is it acceptable to proceed by only checking DEVSTAT.STATE and ignoring the STATEREQ bit? Currently, reading DEVSTAT.STATE indicates that it is in normal mode.

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Polimera
Moderator
Moderator
Moderator
10 likes received 100 replies posted 50 solutions authored

Hello t2355638,

It is sufficient to read the DEVSTAT.STATE for confirmation of PMIC state.

Regards,

Kranthi

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