Announcements

The EV market is bigger and better than ever. Join the EV Webinar to find out how you could best utiilize Power Management ICs for EVs.

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

Power Management ICs Forum Discussions

nsyed
Level 5
Level 5
50 sign-ins First solution authored 25 sign-ins
Can you please confirm if my understanding below is correct for TLF35584 SPI communication

Host MCU should have the below SPI clock settings ? Is the understanding correct ?

CPOL = 0 (Clock Polarity in Idle State = Logic Low)
CPHA = 0 (Data sampled on rising edge and shifted out on the falling edge)
0 Likes
1 Solution
cwunder
Employee
Employee
25 likes received 25 solutions authored 100 sign-ins
nadeem_syed wrote:
Can you please confirm if my understanding below is correct for TLF35584 SPI communication

Host MCU should have the below SPI clock settings ? Is the understanding correct ?

CPOL = 0 (Clock Polarity in Idle State = Logic Low)
CPHA = 0 (Data sampled on rising edge and shifted out on the falling edge)

Yes that is correct, and the data transfer length is 16 bits consisting of 1 command bit, 6 address bits, 8 data bits and a parity bit.

View solution in original post

0 Likes
2 Replies
cwunder
Employee
Employee
25 likes received 25 solutions authored 100 sign-ins
nadeem_syed wrote:
Can you please confirm if my understanding below is correct for TLF35584 SPI communication

Host MCU should have the below SPI clock settings ? Is the understanding correct ?

CPOL = 0 (Clock Polarity in Idle State = Logic Low)
CPHA = 0 (Data sampled on rising edge and shifted out on the falling edge)

Yes that is correct, and the data transfer length is 16 bits consisting of 1 command bit, 6 address bits, 8 data bits and a parity bit.
0 Likes
nsyed
Level 5
Level 5
50 sign-ins First solution authored 25 sign-ins
Thank you so much. Appreciate your help
0 Likes