TLF35584 SPI Clock Polarity and Clock phase

[nsyed]

Can you please confirm if my understanding below is correct for TLF35584 SPI communication

Host MCU should have the below SPI clock settings ? Is the understanding correct ?

CPOL = 0 (Clock Polarity in Idle State = Logic Low)
CPHA = 0 (Data sampled on rising edge and shifted out on the falling edge)

[cwunder · Accepted solution]

nadeem_syed wrote:
Can you please confirm if my understanding below is correct for TLF35584 SPI communication

Host MCU should have the below SPI clock settings ? Is the understanding correct ?

CPOL = 0 (Clock Polarity in Idle State = Logic Low)
CPHA = 0 (Data sampled on rising edge and shifted out on the falling edge)

Yes that is correct, and the data transfer length is 16 bits consisting of 1 command bit, 6 address bits, 8 data bits and a parity bit.

[nsyed]

Thank you so much. Appreciate your help