IR38063 Excessive ripple on Powering Intel Arria 10 FPGA

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drudolf
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I am using a IR38063 to power my Intel Arria 10 Design... The initial design was based on the IR38063 Demo Board. I am seeing what seems like excessive ripple on the output. I have used the SupIR_Buck Design Spreadsheet (attached) to modify the original design to lower the max current (8-10A) and to try and represent the number of capacitors in my circuit. (FPGA required) The spreadsheet shows a very good result as far as ripple but the real world design seems to have short spikes on Vout. I am also getting the VOUT_UV_FAULT at .83V which does seem to imply that there is indeed some significant ripple out output. In trying to tune this I have tried different inductors and then swapped the compensator components (as the spreadsheet indicated) and some of the bulk output capacitors to try and minimize ripple (first page line 119) and maximize phase margin (second page line 101). I unfortunately cannot add all the different type caps that are in my system since the tool only allows 3 different values on the output.   Any help as to where to focus would be appreciated. Hints as to how to pick an inductor and numbers of bulk caps would also be appreciated. 
Dan

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Nishanth
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Hello @drudolf ,

Thank you for contributing to the Infineon Community.

We are evaluating the issue.

Can you let us know how much ripple are you getting?

Can you share ripple voltage waveform and schematic?

Regards,

Nishanth

 

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Hi Nishanth,

Please find attached the schematic pages. The .9V regulator is directly based on your IR38063 demo board design with values generated by the spreadsheet. C664 was a 470uF cap that I removed because I couldn't model it with the spreadsheet and it seemed to make the output somewhat worse. The remote sense lines go into pins on the A10 to sense right at the chip. I will get scope captures today and send but I am seeing about 80mV P2P noise/ripple on the .9V with most of it high frequency with pulses of ~200ns. I would think that I may be picking up system noise but the regulator seems to also be detecting undervoltage of about .83V as I said above. I tried a second board configured identically and is was a little worse with is giving an UVP fault down to .8V.

Dan

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Screenshots attached.

Dan

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Nishanth
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Hello @drudolf ,

100mV of the buffer is usually recommended for VOUT_UV_FAULT LIMIT due to the noise in the digitized Vsense signal.

Ripple seems to be on the higher side. This can be due to the oscillation in the output.

  1. Can you provide us the bode plot for the board if available?
  2. Inductor ripple percentage considered in the Excel design tool is set at 20%. The recommended value is 30%. Is there any specific reason for considering 20%?
  3. Can you provide the part numbers of the input and output capacitors used?
  4. Can you check for any jitter appearing in the switch node waveform?

Regards,

Nishanth

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