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SJZ
Level 1
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10 sign-ins 5 likes given 5 replies posted

Hello,

I have been trying to simulate the ICE3PCS01G in CCM for 2.5kW PFC.

I have calculated Inductor and Capacitor values using the design guide of the controller. 

I have been able to run the controller in CCM with a Cout value of 3.37mF (getting stable after 150ms as seen in the attached screenshot)  but the Cout value is too high for the design. 

I want to run the simulation in CCM for a lower value(~680uF) considering Holdup requirements as 10ms and Vout holdup of 300V. But the simulation is getting disturbed/ not working with desired values. 

Is there anything that I am missing here to get the correct output?

 

Regards,

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Meghana
Moderator
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50 likes received 100 solutions authored 10 likes given

Hello Sajal,

I see that the BOP and BOFO pins are not connected rightly. Either you can try to replicate the circuit from the EVAL_2K5W_CCM_4P_V3 or modify as per the datasheet recommendation. 

https://www.infineon.com/dgdl/Infineon-ICE3PCS01-DS-v03_00-EN.pdf?fileId=db3a304329a0f6ee0129a67ae8c...

Also there is a poweresim simulation model for the same device. The tool also redesigns the circuit based on your inputs. Please have a look. 

https://infineon.poweresim.com/index2.jsp?topologytype=69&NewDesign=true

Kindly try this and let us know if you still face any issue.

Regards

Meghana R

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13 Replies
Meghana
Moderator
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50 likes received 100 solutions authored 10 likes given

Hello @SJZ ,

Please confirm the input voltage specifications. We shall try simulating your use case  and suggest the change. 

Regards

Meghana R

SJZ
Level 1
Level 1
10 sign-ins 5 likes given 5 replies posted

Hello Meghana,

Any updates on this?

still waiting for your reply.

Regards,

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SJZ
Level 1
Level 1
10 sign-ins 5 likes given 5 replies posted

Hello Meghana,

Input Voltage Range should be universal - from 85Vac to 265Vac, typically 230Vrms.

Thanks and Regards,

Sajal

 

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Meghana
Moderator
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50 likes received 100 solutions authored 10 likes given

Hello Sajal,

If you are decreasing just the capacitance value, for the same switching frequency, then that will result in higher ripple on the output side. Can you please share us the zoomed view of both output voltage and current. 

Regards

Meghana 

SJZ
Level 1
Level 1
10 sign-ins 5 likes given 5 replies posted

Hello Meghana,

I have attached the zoomed-in picture of output voltage and current.

13245.PNG)

Vout _max and Vout_min are somewhere close to 437V and 389V respectively.

Iout_max and Iout min are close to 6.83A and 6.14A respectively. 

Regards,

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SJZ
Level 1
Level 1
10 sign-ins 5 likes given 5 replies posted

Hello Meghana,

 I have sent the zoomed in pictures of output current and voltage days ago,

Waiting for the reply.

Also, I was already successfully able to simulate PFC with the same specifications using a ti controller IC with a 680uF output capacitor value.

But we have placed the order for and want to design with Infineon ICE3PCS01 IC, using 680uF capacitor which I want to correctly simulate which I want help with.

 

Regards,

Sajal

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Meghana
Moderator
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50 likes received 100 solutions authored 10 likes given

Hello Sajal,

The bulk capacitance has to basically fullfil below two requirements:

1. Limit the output double line frequency ripple

2. Provide the required holdup time

In your design, 680uF fullfils the holdup requirement but its not sufficient enough to limit the output voltage ripple. 

When the output ripple is higher, in order to regulate the output voltage, we can introduce some dynamic compensation in the control loop, i.e., the ripple is estimated and compensated in the control loop to have better regulation. Unfortunately, ICE3PCS01G does not include such dynamic compensation. 

ICE2PCS01G do have this enhance dynamic compensation which is enabled whenever output ripple >±5% . Similar feature might be available in other competitor IC's which might have given you the better regulation. But it is important to note two points here,

1. This compensation methods are only preferred to support the transient conditions like step load change/ step input change and not during steady state. Steady state ripple should be controlled by the output capacitance.

2. Enhance dynamic compensation distorts the AC input current, which might be acceptable if its for short duration. But if used through out your steady state operation, it increases the input current THD greatly.

Considering above impacts, we still recommend you to use the designed value of 3.3mF at your converter output to obtain the desired results. 

If this solution does not work for you, then please share us more details about your application requirements to suggest a suitable design solution. 

Regards

Meghana R

 

SJZ
Level 1
Level 1
10 sign-ins 5 likes given 5 replies posted

Hello Meghana,

First of all thanks a lot for the explanation. This clears all the confusion I have been having regarding the ICE3PCS01G IC.

However, Just one more question:

eval_2k5w_ccm_4p_v3/  In this CCM reference design for same power rating(2.5kW), frequency(65kHz) and IC, output capacitor value of 1.12mF is used.

2k5wrefdsn.PNG

But I am unable to run the design with the same capacitance. (Simulation result attached below)

1.12mF_infineon_2K5W_refdesign_sim.PNG

 

How can I change my design to simulate for 1.12mF of output capacitor value as in the reference design? 

 

Thanks and Regards,

Sajal

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Meghana
Moderator
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50 likes received 100 solutions authored 10 likes given

Hello Sajal,

Attached is the measurements from EVAL_2K5W_CCM_4P_V3, at a scale of 100V/div. It can be noticed that the output has considerable amount of ripple even in the evaluation board. Your result might have looked different because of the Axis scale. Request you to run the simulation with 100V/div scale and then compare the results. 

Meghana_0-1649063949666.png

 

Can you please let me know what would be the load for this PFC converter. Acceptable ripple value depends on the load. Hence before finalizing the capacitor value, please consider if the connected load could withstand this ripple. 

Also can you please let me know why BOFO pin is been connected to the fixed voltage, instead of PWM feedback?

 

Regards

Meghana R

SJZ
Level 1
Level 1
10 sign-ins 5 likes given 5 replies posted

Hello Meghana,

>> Yes, I can see that output has a considerable ripple.

But as you can see in my previous image, even if the output waveform is considerable, the waveforms below [ Gate, inductor current(I_Vin) ] are getting distorted in simulation with an output capacitor size of 1.12mF. Also you can see Gate is turning off multiple times also the duty cycle is improper.

3872.PNG

 

3873.PNG

>>  Considering load as 64 ohms as we are designing for 2.5kW power rating with 400V output voltage and 6.25A output current. Is that correct?

There will be a DC-DC converter after this stage before the load. 

 

Thanks and Regards,

Sajal

 

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Meghana
Moderator
Moderator
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50 likes received 100 solutions authored 10 likes given

Hello Sajal,

Yes. It is right to consider 64ohms to load the converter with 2.5kW at 400V .

Can you please run the simulation after removing the capacitor and diode connected on the Isense pin and share the observations. 

Regards

Meghana R

 

SJZ
Level 1
Level 1
10 sign-ins 5 likes given 5 replies posted

Hello Meghana,

I have attached the simulation result after removing diode and capacitor on Isense pin below:

6318.PNG

Regards,

Sajal 

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Meghana
Moderator
Moderator
Moderator
50 likes received 100 solutions authored 10 likes given

Hello Sajal,

I see that the BOP and BOFO pins are not connected rightly. Either you can try to replicate the circuit from the EVAL_2K5W_CCM_4P_V3 or modify as per the datasheet recommendation. 

https://www.infineon.com/dgdl/Infineon-ICE3PCS01-DS-v03_00-EN.pdf?fileId=db3a304329a0f6ee0129a67ae8c...

Also there is a poweresim simulation model for the same device. The tool also redesigns the circuit based on your inputs. Please have a look. 

https://infineon.poweresim.com/index2.jsp?topologytype=69&NewDesign=true

Kindly try this and let us know if you still face any issue.

Regards

Meghana R

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