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Hello,
I do redesign to pfc board with your component: IR1155STRPBF that become obsolite.
I chose in ICE2PCS01GXUMA1 as alternative part ,and I have a problem with his application note.
I have some qusetion that I couldn't understand in the example in 3.4:
1. In equation (72) how much Fave need to be smaller than Fsw? (5 times if enough?)
2. In equation (77) G1=+4.52dB IN F=10Hz. if we look at figure 28 we can see that in f=10Hz the gain is very close to 0 from the negative side. Another question is why was chosen 10Hz?
3. I equation (78) I don't understand where the square root comes from?
I will appreciate your help.
BR,
Dror
Solved! Go to Solution.
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Hi @drormo7 ,
Thank you for posting in the Infineon community.
- Typically, the crossover frequency is 5~10 times lower than the switching frequency for compensation.
- Two graphs, one GNON*G23*G4 (dotted) and the other Gv (without dot), are shown in Figure 28. G1 is to compensate for GNON*G23*G4 which is below zero (around 4.52).
Due to PF requirement, inherent PFC dynamic voltage loop compensation is always implemented with low bandwidth to avoid making the response for 2*fL ripple. For example, for 50Hz AC line input, PFC voltage loop bandwidth is normally set below 20Hz. The compensation circuits R4, C2 and C3 optimize the loop gain and phase margin. For initial calculation, it is taken 10Hz.
- The equation for G1 is in Equation 73. Consider the magnitude component when calculating gain because the S parameter is involved. Hence the square root. The value is substituted in equation 73 and shown in equation 77
Please feel free to reach out to us if you need further clarification on this topic.
Regards,
Guruprasad A
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Hi @drormo7 ,
Thank you for posting in the Infineon community.
- Typically, the crossover frequency is 5~10 times lower than the switching frequency for compensation.
- Two graphs, one GNON*G23*G4 (dotted) and the other Gv (without dot), are shown in Figure 28. G1 is to compensate for GNON*G23*G4 which is below zero (around 4.52).
Due to PF requirement, inherent PFC dynamic voltage loop compensation is always implemented with low bandwidth to avoid making the response for 2*fL ripple. For example, for 50Hz AC line input, PFC voltage loop bandwidth is normally set below 20Hz. The compensation circuits R4, C2 and C3 optimize the loop gain and phase margin. For initial calculation, it is taken 10Hz.
- The equation for G1 is in Equation 73. Consider the magnitude component when calculating gain because the S parameter is involved. Hence the square root. The value is substituted in equation 73 and shown in equation 77
Please feel free to reach out to us if you need further clarification on this topic.
Regards,
Guruprasad A
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Hi Guruprasad A,
Thank you for your help.
I have few more questions:
1.For your answer number 2 : G1 gain should be +4.25dB because the GNON*G23*G4 is -4.25dB and the sum will be 0?
2.I can use the graph of figure 28 for my calcultions? or I need to draw a new graph?
If I need to draw I would like to your help how can I do it?
3.About the cross over frequency in equation(77) the 10 Hz is can be used of AC line of 60Hz or it good only for 50Hz?
4.For your answer number 3 I was confused the equation with the square root is in 78.
I don't understand why there is a square root?
Thank you so much for your help!
Regards,
Dror
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Hi @drormo7 ,
1. The basic objective is to give enough phase margin. Therefore, to begin take G1 gain to compensate for GNON*G23*G4.
2. If a design example is similar to your requirement, use the same graph else, using your calculations, plot the graph.
3. It holds good for 60Hz also.
4. I apologize for the misunderstanding; I meant Since Equation is in S Domain.
Regards,
Guruprasad A
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I have a few more questions:
1. In the note of equation(59) write the KFQ mentioned in the datasheet and I can't found it.Can you tell me where I can found it?
2. In the same subject in equation (37) KFQ=9.1 and in equation (59) kfq=4.34 .what is right?
BR,
Dror
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