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I disabled windowdog and can enter normal status normally. When windowdog is enabled, it is configured as WDI dog feeding mode and normal dog feeding, but it cannot enter the normal state. The STATE bit of DEVSTAT is always 001, not be set to 010, and the ROT is always high, and there is no sign of resetting.
What is the reason?
Solved! Go to Solution.
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Hi,
@liwen wrote:4. Disabling the watchdog can make the normal state transition, and reconfiguring the watchdog will cause problems, Is there any fault I didn't notice? I'm confused
Normally, if you can go to normal mode by disabled watchdog and cannot go to normal mode from INIT mode by enabled watchdog. It means failure has been detected. Please check in your circuit.
PS: ROT stays always high in INIT mode (STATE bit 001).
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Hi,
please supplement the whole name of 35584 pmic chip.
BR,
Xiangrui
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tlf35584QVVS1
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Hi li wen,
1. Now the STATE bit of DEVSTAT is 001. It means that you are in INIT mode. If you want to go to normal mode, you have to provide a valid SPI command “Go to NORMAL” (valid with chip select high at pin SCS).
2. Reset pin ROT stays HIGH as the post regulators are already active in INIT state.
3. A delay of more than 60µs after the provided services has to be considered to ensure device goes to normal mode.
BR,
Xiangrui
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1. I send data 0xABD5 and 0xAC2B, and write 0xEA and 0x15 to Devctrl and Devctrln registers respectively. My sending data is manually operated SCS, which is pulled low before sending and set high after sending
2. ROT level is always high
3. After sending the second data, I delayed 80 µs and than get the DEVSTAT value, and found that the STATE bit was still 001
4. I also tried to send the go to normal command in the watchdog close time according to the instructions in the data sheet (that is, first trigger the WDI falling edge, and then send two data), and found that the STATE bit is still 001
5. I also tried to turn off several power supplies. By reading the values of Devctrl and Devctrln registers, I found that the values were written in, but reading DEVSTAT, I found that the power status bits were still 1, and the power supply was not turned off
6. The key point is that I can turn off the power supply and state transfer in the way of disabling the watchdog. Is it the influence of the window watchdog? How is it affected without resetting?
It's a little urgent.Please reply as soon as possible.Thank you very much!
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Hi,
Please refer to the diagram above to check each Pins. (for example ROT stays high is correct.)
If you cannot go to normal mode in this way. Here are some possible reasons:
1. wake up or enable invalid
2. failure occurs
BR,
Xiangrui
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1. I requested the state transition in this way, but it was not successful.
2. I saw some failures. They all involved that the ROT would be pulled down, but they are not applicable to the current situation where the ROT has been high.
3. The watchdog fault counter has not overflowed, which is normal in the process of feeding dogs.
4. Disabling the watchdog can make the normal state transition, and reconfiguring the watchdog will cause problems, Is there any fault I didn't notice? I'm confused
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Hi,
@liwen wrote:4. Disabling the watchdog can make the normal state transition, and reconfiguring the watchdog will cause problems, Is there any fault I didn't notice? I'm confused
Normally, if you can go to normal mode by disabled watchdog and cannot go to normal mode from INIT mode by enabled watchdog. It means failure has been detected. Please check in your circuit.
PS: ROT stays always high in INIT mode (STATE bit 001).