Hi. I'm looking for examples of using Verilog and expose/consume data that is shared with the CPU. All examples showing verilog and datapath's seem to skip that part. I'm trying to write a component that receives a 24-bit pulse train and exposes it to the CPU for use with a PID controller. Initially, I thought I would clock these values into a verilog reg and then latch them to a register that I could read from the CPU. It also appears that I could skip the entire part and shift them into a datapath and read it from the CPU. But, no examples of anything like this exists (reading verilog values from the CPU). Also, I need to output 5 configuration lines. I thought a control register would do it, so I mapped 5 lines of the control register to the outputs (on my symbol definition). When I build the API side, I always get a "_REMOVED = 1u" for my symbol. FYI: The component I trying to use is TI's ADS1274 - a 24-bit ADC with 4 simulatenous outputs. Any advice, or any good place to get info about DataPaths that aren't already in the documentation (yeah, I already read the manuals provided).
