Anonymous
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Feb 05, 2018
02:53 AM
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Feb 05, 2018
02:53 AM
Is there any option to produce 500 ms delay in psoc by using verilog without giving clock as input signal
1 Reply
Feb 11, 2018
08:21 PM
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Feb 11, 2018
08:21 PM
Can you please mention about your application in which you have such requirement.Generally gates ,FFs are sufficient for creating delays