PSoC™ Creator & Designer Forum Discussions
Found a bug in code generation of ImageCraft compiler.
Due to the poor forum software here I posted it already in another forum with the drawback that it was not reacted on. Yes, I see we cannot have everything, good software AND good support (sigh).
So here is the link to my primary post http://www.psocdeveloper.com/forums/viewtopic.php?f=28&t=11117&p=43604#p43604
Bob
Show LessFirst question is, how I can report minor errors such as typos.
I once commented on the article:
http://www.cypress.com/?id=4&rID=41079
that it should be "count++" instead of i++ under item 2.
I got the response that I could open an issue.
I find that strange, why should I go through a long process, as I understand the
intention of the example, I do not care whether it is fixed or not.
I found another trivial error in the I2C_<x>_MASTER.c file:
* Function Name: I2C_2_MasterReadBuf
********************************************************************************
*
* Summary:
* Automatically writes an entire buffer of data to a slave device.
This documentation is wrong, it is for the MasterWriteBuf function, for this one it should be
"reads an entire buffer from the slave device" .
Finally, one question, of how one could use version control with
PSoC projects.
Is there a way to represent
the schematic and the system configuration (cydwr) has text file so that it can ve compared and tracked, e.g. with CVS?
Currently I debug code (PSoC 3) in parallel on the development kit and the target hardware.
As the pins are more easily accessible on the development kit, it is useful to debug things there.
However, pin assignments are different, so I cannot just switch the device type in the same project.
For source code I can use WinMerge etc. to get changes between the two workspaces.
But component configurations have to be manually done.
Any solution for this?
Andreas
Show LessThis post is meant to distribute the first order DeltaSigma modulator component constructed from the SC/CT blocks. This component exposes the useful DeltaSigma modulator functionality of the SC/CT blocks in an easy to use way. Provide a clock (5 Khz to 4 Mhz), a reference (the 1.024 volt SC/CT block reference is the only suitable reference that does not require buffering) and an analog input in order to use the modulator. The component also exposes the integrator reset for incremental mode, as well as the analog output of the integrator for educational or creative purposes. There is currently no datasheet for the component, but all that is required is to call the _Start() API in order to use the modulator.
The modulator has 2 input ranges. Vref +/- 2*Vref and Vref +/- 0.5*Vref. When using the 1.024 reference, the modulator input ranges are 0 – 3.072 volts and 0.512 – 1.536 volts.
Rev *A: The component now correctly handles different clock sources and low voltage boost pump operation. Please use this version.
This component is not "complete" in the sense that it does not contain a datasheet, but since I am not sure when I will get around to generating a datasheet for this component and it has value even with a half-finished set of documentation, I am releasing it anyway. The zip archive includes an breif description of the component and the connections, a .cycomp archive of the component, and a bundle example project.
Show LessI would like to simplify my hardware design for raising 2 interrupts events with a single digital input pin to detect pulse edges. So my idea is to use digital input hardware pin to detect pulse falling edge while a isr component to detect a rising edge by connecting to the digital input pin. This trys to raise 2 seperated interrupt events. Make clear that it is not to raise a single event with detecting rising and falling edge. The topdesign is shown as following diagram. Is this going to work? Has anyone have any this experience?
Qingshan
Show LessHey guys
Could you please help me in sloving following error:
CAUTION boot.asm is older than boot.tpl or is missing
CAUTION you may need to generate source in PSoC Designer
!E ./boot.asm(0): cannot open './boot.asm' for input
C:\PROGRA~1\CYPRES~1\PSOCDE~1\tools\make: *** [obj/boot.o] Error 1
Thanks
Show LessI have bookmarked what seemed to be the PSoC Today home page: http://www.cypress.com/?rID=60521 . But it shows now changes since last November. By accident (because Chris Keeser linked some videos on YouTube) I found out that there has been a slew of new episodes since then which are linked only in the video library...
So for anybody looking for new and interesting stuff, head over to http://video.cypress.com/video-library/video/Web-Series and learn something new and interesting...
Show LessI would like to simplify my hardware design for raising 2 interrupts events with a single digital input pin to detect pulse edges. So my idea is to use digital input hardware pin to detect pulse falling edge while a isr component to detect a rising edge by connecting to the digital input pin. This trys to raise 2 seperated interrupt events. Make clear that it is not to raise a single event with detecting rising and falling edge. The topdesign is shown as following diagram. Is this going to work? Has anyone have any this experience?
Qingshan
Show LessI fiddled with the Integer Square Root Calculator a little bit, and by modifying the underlying datapath algorithm slightly, was able to double the resolution of the calculated square root. I've called the new component a "Fixed-Point Square Root Calculator." Instead of a 32-bit integer resulting in a 16-bit integer square root, a 32-bit integer will now produce a 32-bit square root in Q16.16 format (16 integer bits and 16 fractional bits). The included datasheet has more info on how to use the fixed-point math. Here's a quick overview of the component:
8, 16, 24 & 32 bits.
In 32-bit mode, takes a 32-bit input and calculates a 32-bit fixed-point (Q16.16) square root in at most 220 cycles (slower than the Integer Square Root Calculator, but for twice the resolution!).
CPU-mode for easy firmware interaction, DMA-mode for HW-controlled, CPU-free operation.
220 cycles in 32-bit mode, 164 cycles in 24-bit mode, 108 cycles in 16-bit mode, and 52 cycles in 8-bit mode.
Show LessOk, i've read the release and component notes for the MDIO. nice job.
but ...
this is only part of an MII/RMII solution. is the other coming very soon or do we start to roll our own? do we think a set of UDBs ( 2 or 4?) can keep up with 25/50Mhz ethernet traffic needed for MII/RMII? by the time we are done a full MII/RMII how many UDBs will be used up? will we have any left to do any work with the data?
-Ed
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