PSoC™ Creator & Designer Forum Discussions

Hi,

I 'm new to PSoC and want to dig deeper into it So I bought a PSoC 4 pioneer kit as a starting point.

Now, I want to go for my 'real' first own design. This design uses a shift register component.

I've some questions:

1) It seems a counter is necessary to detect if the desired number of bits have been shifted, right?

2) I want to generate an interrupt if a new byte has been loaded from the FIFO into the shift register. I don't use the load input signal, but it seems that the load interrupt output can still be used for that purpose, right?

3) Is it possible to access the shift register status register (or the underlying UDB) by hardware? I want to detect if the FIFO is empty.

Regards,

Ralf

In the PSOC 4 datasheet the CM input range for SAR is stipulated as

Vss to Vdda, should it be Vssa to Vdda ?

Also in TRM no discussion mentioned if SAR is a R ladder solution. Reason

I ask is the linearity specs are only speced for Vref >= 1 V, but if architecture

is R ladder one would think much lower Vrefs would still experience the same

linearity performance ? Or is this related to switch performance in the ladder

mux to decision comparator ?

Regards, Dana.

Hi, I am trying to bring up a SDCARD useing Element14 design on PSOC 4, seeed shield, and having issues.

On that forum last post was Sept, there was a Mathew Buza and Sriram Vikraman Sithalakshmi doing most of the posts.

Does anyone know how to get in touch with either of these people ?

Regards, Dana.

I am trying to control a digital multiplexer based on input from a serial command. I can't figure out how to command the multiplexer selection through the software (main.c). How do I do that? What document should I be looking at to determine this?

Can we develop our own bootloader component withour having communication interace code inbuilt in it?

If yes then what is best way to start for creating using Creator ide?

I've tried to read through all the posts in the forum that appear to discuss the UDB Editor in PSOC Creator 3.0

I didn't "reply" to any of them, since no ONE has been designated a central clearinghouse for trouble reports on the UDB Editor.

I apologize for the post, please delete if wrong type/format.

I've seen posts from some about specific problems and some requests of "how do we report problems". I'm not sure I, or others, understand any tracking or support procedure for something like this. I don't think we need to open a "MyCase" for each individual problem and I know of no way of seeing all open or closed bug reports to avoid duplication. If you want to post them to this thread for Robyn to forward to Development team or for Nick (NSF-Cypress?) to reply to.

I've seen some posts by Dana, psoc73, bob, nick, spider... etc but think most of my issues/questions have not been addressed.

I came late to PSOC Creator 3.0 (PC 3.0)because we are primarily working with Christmas Lighting products and my busy season has just ended. I couldn't take a chance of working with a new environment with my production code late in the season.

All in all I think PC 3.0 is a VAST improvement and applaud Cypress on this major release.

Once over the learning curve I find the UDB Editor to be a great tool in the making. I don't think it is there yet, but hopefully the development team can finish it up soon.

In the tutorials they talk about "advanced features can then be added by copying the verilog ..." or something close to that. But they never discuss what they are calling advanced.

Here is a short list of the 'problems' I'm having so far:

1) I can't locate any way to control most of the features of the FIFOs. I see several FIFO properties but can't find the way to change the FIFO to input vs output (bus vs udb sourcing). Am i overlooking something. Having to copy the verilog and modify it will be a development headache.

2) If you add a control or status register to the USB Design DON'T delete the unused bits for 'cleanliness'. If you do you will get a 'Net_1' undefined message. Just leave unused bits there.

3) If you add a Count7 register I can set some of the inputs (reset, enable, etc.) but can't set the clock, and more importantly I can find no way to USE the Count7_tc output. I believe the verilog is being generated correctly. It makes a wire and adds it to the Count7 module definition but if I try to use the signal as part of ANY expression then I get an error saying it doesn't exist and, of course, the verilog becomes non-generated. Take out the expression and the verilog comes back. So I think it is an internal table lookup problem and not a real generation of verilog problem.

#1 is major IMHO, #2 is cosmetic, #3 is major. Altogether I don't see how I can use the UDB Editor for production code until these types of problems are fixed. I've invested a lot of time over the holidays learning the GUI and visually designing the state machines and examining the generated verilog to see how they do it. It is BEAUTIFUL and VERY powerful, and I want it to work soon!!!

-Ed