PSoC™ Creator & Designer Forum Discussions
Is somebody else having problem with the gmtime() function after the PSoC Creator 3.1 upgrade? The code below is not completing as the gmtime() function is never returning. It used to work fine before the update...
#include <project.h> #include <time.h> /*! * Starts the Application. */ int main() { time_t seconds = 1420663532; struct tm *ts = gmtime(&seconds); return 0; }Show Less
Hello everyone,
I have developed a capsense board with 5 buttons & a slider.
I intend to use these boards for the electrical switching applications like light, fan with regulators T.V. etc.
I want to know will they function like the normal mechanical swiches or not for longer durational operations.
I wish to know the +ve & -ve effects on the board if I keep the apps running continuously for longer durations (suppose for complete 1 day).
Will that degrade the performance of the board with such operating over the period of time?
If it does what are the remedies you would suggest me?
Thanks & Regards-
Amit
Show LessI was running debug sessions and noted the debugger started at start of code in main.c
Now, for some reason, it starts in "cm3start.c" ??? Did I inadvertantly click some setting instead of the debug btton or is this some automated feature that it decides to start from somewhere else?
Show LessMigrating 2.2 project to 3.0.
Used the more advanced clock editor to match our hand modified settings.
Writes to CYREG_FASTCLK_XMHZ_CFG0 and CYREG_FASTCLK_XMHZ_CSR are identical.
Code always ends up in the error routine ?
Tried all kinds of different settings, configurations. Nothing helped...
Anyone else having these issues ?
Show LessHey guys i am interfacing arduino board with capsense MBR3,I have found the example project and was just going through the explaination. I didn't understand as in I have to configure capsense kit using arduino over I2C so whats EZ click used for?Cant I configure the capsense MBR3 through EZ click and then plug the sheild n to arduino?
Show LessI very often to create a new project by copying it fragments from previous projects.
However, I found the problem:
I needed more pins, and I did not create anything and copied some of the other project.
Both projects use PSoC Creator 3.0 SP2 (3.0.0.3140)
The result - in the screenshot below.
It certainly is not terrible, all the problems are visible and they are easy to fix, but maybe this is just the tip of the iceberg.
So I have a question:
Can I copy components from one project to another?
I note in the example that the RTD_GetTemperature() API returns a 32 bit unsigned int.
I have written code based on the example and find that I cannot display values below 0. Casting the int as a foat does not convert the negative (I assume 2's complement) value into the appropriate negative temperature value.
Is there a convenient conversion or do we need to manually do a 2's complement on the resistance value?
rtdRes = (rtdVoltage * CAL_REF_RESISTOR / rtdCalVoltage) * 1000; //convert to mOhms
rtdTemp = RTD_GetTemperature(rtdRes); //Returns 2's complement value when rtdRes < 100,000 mOhms (PT100)
tempdisp = (float) (rtdTemp/100.0);
sprintf(strbuf,"%3.2f%c",tempdisp,13);
RS232_PutString(strbuf);
Show LessI try the example project - emfile_example
I use - PSoc creator 3.0
When I try to build the program (before do any change to code)
I get the following output:
Log file for this session is located at: C:\Users\User\AppData\Local\Temp\PSoC Creator-000.log
--------------- Build Started: 12/23/2014 12:35:10 Project: emFile_Example01, Configuration: DP8051 Keil 9.51 Debug ---------------
cydsfit.exe "-.appdatapath" "C:\Users\User\AppData\Local\Cypress Semiconductor\PSoC Creator\3.0" "-.fdsnotice" "-.fdswarpdepfile=warp_dependencies.txt" "-.fdselabdepfile=elab_dependencies.txt" "-.fdsbldfile=generated_files.txt" "-p" "C:\Users\User\Dropbox\PSoC Creator\Design01\emFile_Example01.cydsn\emFile_Example01.cyprj" "-d" "CY8C3866AXI-040" "-s" "C:\Users\User\Dropbox\PSoC Creator\Design01\emFile_Example01.cydsn\Generated_Source\PSoC3" "--" "-yv2" "-v3" "-ygs" "-q10" "-o2" "-.fftcfgtype=BE"
Elaborating Design...
HDL Generation ...
Synthesis ...
Place and Route ...
Tech mapping ...
Info: mpr.M0037: Unused pieces of the design have been optimized out. See the Tech mapping section of the report file for details. (App=cydsfit)
Analog Placement ...
Analog Routing ...
Analog Code Generation ...
Digital Placement ...
Digital Routing ...
Bitstream Generation ...
Static timing analysis ...
API Generation ...
Dependency Generation ...
Clean Temporary Files ...
c51.exe .\main.c NOIV LARGE MODDP2 OMF2 VB(1) PR(.\DP8051\DP8051_Keil_951\Debug\main.lst) CD DB NOIP "OT(2, Size)" "INCDIR(., .\Generated_Source\PSoC3)" OJ(.\DP8051\DP8051_Keil_951\Debug\main.obj)
WARNING: .\Generated_Source\PSoC3\emFile.h:23: can't open file 'MMC_X_HW.h'
WARNING: .\main.c:32: can't open file 'FS.h'
WARNING: .\main.c:34: can't open file 'Global.h'
ERROR: .\main.c:40: syntax error near 'step', expected ')'
ERROR: .\main.c:50: 'step': undefined identifier
ERROR: .\main.c:52: 'str': undefined identifier
ERROR: .\main.c:64: 'U16': undefined identifier
ERROR: .\main.c:64: syntax error near 'step'
ERROR: .\main.c:65: 'FS_FILE': undefined identifier
The command 'c51.exe' failed with exit code '2'.
--------------- Build Failed: 12/23/2014 12:35:38 ---------------
--------------- Build Started: 12/23/2014 12:36:34 Project: emFile_Example01, Configuration: DP8051 Keil 9.51 Debug ---------------
The code generation step is up to date.
c51.exe .\main.c NOIV LARGE MODDP2 OMF2 VB(1) PR(.\DP8051\DP8051_Keil_951\Debug\main.lst) CD DB NOIP "OT(2, Size)" "INCDIR(., .\Generated_Source\PSoC3)" OJ(.\DP8051\DP8051_Keil_951\Debug\main.obj)
WARNING: .\Generated_Source\PSoC3\emFile.h:23: can't open file 'MMC_X_HW.h'
WARNING: .\main.c:32: can't open file 'FS.h'
WARNING: .\main.c:34: can't open file 'Global.h'
ERROR: .\main.c:40: syntax error near 'step', expected ')'
ERROR: .\main.c:50: 'step': undefined identifier
ERROR: .\main.c:52: 'str': undefined identifier
ERROR: .\main.c:64: 'U16': undefined identifier
ERROR: .\main.c:64: syntax error near 'step'
ERROR: .\main.c:65: 'FS_FILE': undefined identifier
The command 'c51.exe' failed with exit code '2'.
--------------- Build Failed: 12/23/2014 12:36:35 ---------------
--------------- Build Started: 12/23/2014 13:00:11 Project: emFile_Example02, Configuration: DP8051 Keil 9.51 Debug ---------------
cydsfit.exe "-.appdatapath" "C:\Users\User\AppData\Local\Cypress Semiconductor\PSoC Creator\3.0" "-.fdsnotice" "-.fdswarpdepfile=warp_dependencies.txt" "-.fdselabdepfile=elab_dependencies.txt" "-.fdsbldfile=generated_files.txt" "-p" "C:\Users\User\Dropbox\PSoC Creator\Design01\emFile_Example02.cydsn\emFile_Example02.cyprj" "-d" "CY8C3866AXI-040" "-s" "C:\Users\User\Dropbox\PSoC Creator\Design01\emFile_Example02.cydsn\Generated_Source\PSoC3" "--" "-yv2" "-v3" "-ygs" "-q10" "-o2" "-.fftcfgtype=BE"
Elaborating Design...
HDL Generation ...
Synthesis ...
Place and Route ...
Tech mapping ...
Info: mpr.M0037: Unused pieces of the design have been optimized out. See the Tech mapping section of the report file for details. (App=cydsfit)
Analog Placement ...
Analog Routing ...
Analog Code Generation ...
Digital Placement ...
Digital Routing ...
Bitstream Generation ...
Static timing analysis ...
API Generation ...
Dependency Generation ...
Clean Temporary Files ...
c51.exe .\main.c NOIV LARGE MODDP2 OMF2 VB(1) PR(.\DP8051\DP8051_Keil_951\Debug\main.lst) CD DB NOIP "OT(2, Size)" "INCDIR(., .\Generated_Source\PSoC3)" OJ(.\DP8051\DP8051_Keil_951\Debug\main.obj)
WARNING: .\Generated_Source\PSoC3\emFile.h:23: can't open file 'MMC_X_HW.h'
WARNING: .\main.c:32: can't open file 'FS.h'
WARNING: .\main.c:34: can't open file 'Global.h'
ERROR: .\main.c:40: syntax error near 'step', expected ')'
ERROR: .\main.c:50: 'step': undefined identifier
ERROR: .\main.c:52: 'str': undefined identifier
ERROR: .\main.c:64: 'U16': undefined identifier
ERROR: .\main.c:64: syntax error near 'step'
ERROR: .\main.c:65: 'FS_FILE': undefined identifier
The command 'c51.exe' failed with exit code '2'.
--------------- Build Failed: 12/23/2014 13:00:41 ---------------
Warning: prj.M0213: A build is required before the project 'emFile_Example02' can be exported. Would you like to build and continue with the export now?
NO
Yoni
Show LessUsing the CYC8KIT-050, I am trying to multiplex two analog inputs to a ADC_SAR and have the two channels' input samples go to separate arrays. Disclosure: I have had a case open on this for two weeks but the only response I got was a lame example of a single analog input pin sending 200 samples to Array1 and then 200 samples to Array2 using two TDs. That's not what I need to do. I need one sample from input A, then a sample from input B ... repeat until 2040 samples are collected in each array ( DMA_A[2040] and DMA_B[2040] ). Later I need to time align the samples in a FIR Filter (not shown in this simplified version). My problem is that I seem to only write to the first element of each array -- at best.
In the TopDesign I am using a LUT to select the MUX input. I'm using a countdown timer to generate an Interrupt when we have 4080 samples collected. Each EOC ticks down the timer and generates a new SOC delayed by 1.5us through the PWM. I'm using two TDs, one for each array.
In the project attached, the DMA_Done ISR serves no purpose. In another version, I sent one sample to a single variable using one TD, then used the ISR to load it into either DMA_A or DMA_B. I checked to see if our sample count was even or odd to determine which array to load like this:
CY_ISR_PROTO(DMA_Done);
CY_ISR(DMA_Done) // interrupt handler for DMA done
{
if (adc_count & 1) // See if the array offset is even or odd
DMA_B[adc_count] = adc_read; // it's odd -- Load Right Channel
else
DMA_A[adc_count] = adc_read; // it's even -- Load Left Channel
adc_count++; // adc_count is declared as volatile
DMA_Done_flag = 1;
}
In the while (forever) loop, I print the values of DMA_A elements 1,2,and 3 on the top row of the LCD. I print DMA_B elements 1,2,3 on the sencond row. NOTE: To test this you must assure that at least one channel's input connection to the potentiometer on P3[6] in the cydwr. Note that the dummy initalizations in lines 169,170 do not get overwritten by data as shown on the LCD.
If this method is not feasible, perhaps someone could suggest a C++ structure that could separate every other element from a single array without using CPU cycles in a for loop. The single starting array would be:
sampleA[1],sampleB[1],sampleA[2],sampleB[2],sampleA[3],sampleB[3]...
But my FIR Filter will have to see:
sampleA[1],sampleA[2],sampleA[3]... in channel A, and
sampleB[1],sampleB[2],sampleB[3]... in channel B
Workspace Bundle attached. Thank you.
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