PSoC™ Creator & Designer Forum Discussions
Hi,
I'm working with the CMSIS DSP libraries on a PSoC 5LP. The CMSIS lookup tables need a lot of program space (~93% of flash used with only minimal application code), so I decided to enable 'link time optimization'. This punched the flash usage to below 10%.
Now, I want to use functions like sprintf() etc, but this throws me the 'issue 1' error described here:
So, even if the knowledge base article is tagged for PSoC 4, the solution posted at the end of the article also applies to PSoC 5LP:
disable LTO for Cm3Start.c file. This adds only ~1.5% percent to the flash usage, so now I'm at ~10% flash usage, but at least the application compiles without errors.
Hope this will help other users if they encounter the same problem.
@Cypress:
- Please remove the PSoC 4 tag of the KBA - it seems that this error also applies to PSoC 5LP.
- Also please review the KBA statement which states that the LTO settings will be removed on PSoC Creator 3.2 and later. I'm on 3.3 SP1 (3.3.0.7343) and still have those options. Please note: I'm glad that those options are still there, otherwise I'd have to manually remove unused data from CMSIS files - some kind of a No-Go.
- Please review support case #3160570872 to see why 'remove unused sections' isn't enough when using CMSIS - it seems LTO must be used also in this case, otherwise CMSIS will use most of the available memory.
- Also note that the KBA is missleading regarding the solution: the statement 'To resolve this issue in PSoC Creator 3.1 or earlier, turn off LTO for...' is posted for issue 2 (PSoC 4 related), but the same solution also applies for issue 1 (at least the project compiles without errors...).
Regards,
Ralf
Show LessHello,
I am currently working on a project and require development assistance with the USBFS component. I have reviewed the list of contractors provided on the Cypress website and there many. Instead of sending a request to each of the listed contractors that may be able to provide assistance, I'm hoping at least a number of them monitor the Cypress forums.
Overview of the requirement. The project currently implements a USB device which implements a custom interface to a Windows PC using libusb. It also implements an standard audio interface. The requirement is to add another standard audio interface to the USB device. It is easiest to understand the requirement when examining the project.
The project is being developed on the CY8CKIT-059
Regards,
Ron
Show LessThe GCC compiler automatically runs .S files through the pre-processor, while leaving .s files alone before handing them to the assembler.
Is there any way to get PSoC Creator to treat .S files the same way? I added a .S file to my project but it is not being run through the preprocessor.
Show LessI am trying to realize a feature where once the BLE device is powered up, it will connect automatically to a peer device whose address has been stored when it had been connected before.
the BLE device that I am developing acts are a peripheral.
Of course, at the very first time it turns on, it would have no history of a device address to connect to. However, when connected to some peer device, it will store its device address(or something else to identify the partner) in the flash.
In that way, even after a power cycle, my BLE device will load the target device address from flash and try to connect to it.
So far, digging in to the API documents, I've found that the 'whitelist' seems to be one way to realize my objective.
However, I'm curious about a few things here:
Q1. Is whitelist the only chance for me to achieve my goal?
Q2. Connection is made when both the peripheral and central both interact with each other. Therefore I'm assuming that trying to do something on the peripheral side alone is not enough to achieve my goal. Am I right to think that I need to make changes in the central BLE device too?
Show LessHello All,
I am looking to download cy8ckit-042 kit design files/components that can work with PSOC 3.0. Due to some reason, my company has instructed me not to update the PSOC ver 3.0 and because of that, I am unable to use my PSOC Pioneer Kit on the same PC.
Any leads will be appreciated.
Thanks
Ronnie
Show LessI have an open source project that I was looking at and now 2 assigned GPIO (output) pins of a CY8C3246PVI-147 are being reserved for a 32kHz crystal P15[2] and P15[3].
I had enabled the 32kHZ crystal on the Clock configuration page but went back and disabled (unchecked) it but the pins still cannot be used for the previously assigned output function.
Cypress Creator 3.3 SP1 is being used and shows 2 errors that these pins are reserved for the XTAL_32khz clock. How do I regain access to these 2 pins for GPIO usage?
The project's .cydwr file pins assignment page shows the reservation (shown in red) but the project build completes. If I go back to the Clock configuration page and check the box to use the 32kHz crystal and attempt to build the project it fails.
Looks like a bug in PSoC Creator 3.3 SP1 not clearing the reservation display on the cydrw Pins tab for the XTAL_32kHz pins even though that crystal is not being used.
Show LessIs there any way of specifying false paths or other timing exceptions for Warp synthesis in a custom component PSoC design?
I seem to have run into a bit of trouble meeting the timing requirements for a PSoC 5LP design. Specifically the path from the output on a bidirectional GPIO pin back to the input pushes the synthesis over the edge. The input and the output logic are only used in separate modes of the system however so I am hoping to declare this as a false path without the synthesis failing or expending resources optimizing for it.
I do know how to work around the issue with additional buffering however the margins of the design are getting alarmingly tight so any cycles shaved off would be a boon.
Admittedly I am a programmer still very much struggling to get to grips with this HDL business and may well be going about designing and optimizing it all wrong. Incidentally any tips for suitable reading matter on this subject would be much appreciated, ranging from specific PSoC tricks to general hardware design principles.
Show LessDo you really need all those little u's (unsigned designators) everywhere?
I'm very fluent in visually reading "hexadecimal" data. As such, all those little u's are really annoying.
If the array is already type casted with uint8, do we still need to add the u suffix to the data entries?
This slows me down significantly in my coding efficiency.
See below for an example.
--------------------------- too many u's --------------------------------------
/* I2C Read service UUID*/
const uint8 I2CReadUUID[16] = {
0x00u, 0x00u, 0xFBu, 0x34u, 0x9Bu, 0x5Fu, 0x80u, 0x00u, \
0x00u, 0x80u, 0x00u, 0x10u, 0x01u, 0x00u, 0x0Au, 0x00u \
};
---------------------- BETTER and more READABLE ----------------------
/* I2C Read service UUID*/
const uint8 I2CReadUUID[16] = {
0x00, 0x00, 0xFB, 0x34, 0x9B, 0x5F, 0x80, 0x00, \
0x00, 0x80, 0x00, 0x10, 0x01, 0x00, 0x0A, 0x00 \
};
Show LessI find myself drawing logic gates that follow my line of thinking and hopefully reflect the purpose of the logic itself (labeling nets).
Looking at the result it is obvious that this does not result in an optimal circuit.
Will Creator apply boolean algebra to simplify/optimize the actual logic that is programmed in the PSoC chip?
Thanx, Marc.
Show LessI have the CY8CKIT-042-BLE Pioneer Kit. Originally, I had the 3.3 version, and the setup page for creating new projects was new and strange to me. Then I switched to 3.2, and there is still no such an option for the "PSoC 4 Design". What should I do? Go for lower version or 3.2 is okay but I just didn't see the option? The attached is the setup page I have. Thanks!
Show Less