After two years I am just starting again with the PSoC Creator and some things are really bothering me.

My Setup:

- i5-CPU, 16GB RAM, SSD, 64bit Linux Host.

- Win10 Enterprise 64bit in Virtual Machine with 8GB RAM and 4 CPU-cores in Virtualbox.

- PSoC Creator  4.1 (4.1.0.2686)

- CYC8KIT-042-BLE with CY8C4248LQI-BL583

The problem is not the embedded, it is the PSoC Creator!

The Code-completion does not work anymore. I tried to enable different features via Options --> Text Editor --> Inline Diagnostis and Autocomplete. But nothing that I can enable or disable there really changes anything! (Restarted PSoC Creator of course!)

And if that was not already bad enough, the function "Go to Declaration F12" and "Go to Definition Ctrl+F12" is also not working! No error, no message, nothing happens!

I also tried to install the PSoC Creator in a fresh Win7-Virtual machine, with the same results. Right after the installation the F12-function was initially working one time, but after reboot, or when I opened an old project, nothing worked any more.

I was just thinking about ordering the new PSoC-6 with the BLE 5.0 functionality, but not with this performance!

Is there anything I could do to improve the performance?

Has anybody else recognized this behaviour?

Thanks

Andreas

Hi guys,

There is a component named ByteSwap in the project of Music_Creation(an example project included in CY8CKIT-033A).But i can not open the datasheet of it in the component configration(attached is the detail).So how can i get it?

Hi, my name is Guillaume Boucher and I work for a public school. A teacher asked me to deploy the PSoC Creator 4.1 on multiple computers. I can't find a way to do a silent install of this application. The switch "/S" doesn't seems to do anything. Therefore, I decompressed the content of the EXE installer file and manually tried to install every MSI and EXE programs. This time it install fine but when I launch the program, I get multiple errors like this one: "An important piece of PSoC Creator has a problem and may not work correctly. Please restart PSoC Creator.". By the way, I also get these errors when I do a manual (not silent) installation of the program. So, what am I missing here?

Any help would be greatly appreciated!

Guillaume

I'm trying to create a 16-bit adder using the UDB Editor. First of all, is this even possible? It seems that if I want a device with 48 "pins" I may not have enough registers to handle two words of input and one word of output.

Background might help, I guess. I am trying to set up DMA to allow write (at least), and ideally also read, from a 4K array in SRAM on PSOC 5 (and maybe also PSOC 4). I have a 16-bit address bus implemented in two sets of 8 GPIO pins. The access from the external bus is random, and one byte at a time. A R/W pin indicates the direction of data flow, and there are another 8 pins for D0-D7. This currently works fine for writing to a single uint8 in SRAM, but not for being able to address multiple locations based on the GPIO address.

What I think I need is this adder, so I can load it with the base address of the array at startup, and have it add to that the offset into the array coming from the lower 12 bits of the address bus.

I've been looking for indexed DMA solutions, but the documentation on that is really sparse and I still can't see how it would do what I need. As far as I can tell, indexed DMA works if you can get the absolute destination address from somewhere else. I can get the relative offset, but not the absolute address... thus the need (I think) for an adder. I do see that the Keil compiler allows some explicit object positioning in SRAM, but I'm using gcc.

So, the goal I'm currently working towards in the UDB Editor is this adder. It's pretty easy to see how to set up some instructions and state machine states to load A0 from D0, then add A0 to D1 and have the result available from the ALUout. What I can't see is how to correctly make byte or word wide interfaces available in the component so I can connect them to my pins. UDB Designer allows me to add single pin/bit inputs, and it also allows me to add design-wide variables (but the design-wide variables seem to be almost undocumented... what is registered vs. combinatorial? what kinds of expressions are allowed for them?) Come to think of it, I really only need 12 "pins" for the offset address from my GPIO pins. Everything else I can read and write in firmware/software.

To recap, here's what I think I need:

--- in the solution ---

1. Connect AD0-A12 from GPIO pins to the adder component... maybe also connect CS or some other enable signal or clock

2. Configure DMA to use address from adder output as destination

--- when running ---

1. Create 4K uint8 array

2. Set the LO16 of the array start address into the adder

3. (when a new address is available, the adder will be providing a computed absolute corresponding address into the 4K array so DMA read or write requests can source or store the correct byte location)

I've been reading through the AN's on the UDB Editor. I'm not yet finding what I need. I get the impression that I need to use the FIFO registers to load D0 and D1 first, but I still don't see how to load F0 and F1 from hardware inputs. I also dropped a Control Register into the design, but I can't see how to hook that up to anything.

Worst case, I might be able to make this work with an interrupt to copy a single DMA-received byte to the correct location in the buffer, or, I guess I could create an interrupt handler to copy each written byte into the correct place in the array after DMA is complete, but that's a lot messier and I already know the entire CPU-driven data read process isn't fast enough on PSOC 4. Hardware/firmware addressable DMA seems so much more elegant here.   

So, thanks in advance for some pointers on what I'm trying to do, or towards documentation that I should be reading.

Thanks,
Paul

For example, the project (developed on a different PC) uses USBFS 3.20.

The Component Update Tool shows the Current Version as '3.20 (Unknown)' and the New Version as 3.10.

The internet connection is fine.  Both PCs have PSoC Creator 4.1 Update 1.

I'd be grateful if anyone could suggest a method to debug this.

I want to build a simple SR flip-flop that is not synchronized.  Simple two NAND gate design you find in basic logic.  If I use synthesis optimization I get a lovely *Warning* - "Warning-1361: The design contains a combinational loop. Check the design for unintentional latches. Breaking the loop at SR_Feedback1/main_1 --> SR_Feedback1/q" which apparently alters the design for a WARNING.

Looking in the forums, the *fix* is to set synthesis optimization to none, but then the design no longer fits.

So optimization means the synthesizer get to be my mother too?

I am trying to get a CI build going with Jenkins. I followed these instructions to get a headless build working: https://community.cypress.com/docs/DOC-10865

This works fine from a command line or from a batch file, but when I call the same batch files from Jenkins I get the following failure message:

Error: mgr.M0027: Argument passed in is not serializable.

Parameter name: value (App=cyprjmgr)

   at System.Collections.ListDictionaryInternal.Add(Object key, Object value)

   at CyDesigner.Common.Base.CyRsltOrErr`1.get_Value()

   at CyDesigner.Common.Db.DeviceDb.Catalog.CyWcdMgr.get_InstallBaseDir()

   at CyDesigner.Common.Db.DeviceDb.Catalog.CyDcPlugin.get_DeviceDataPath()

   at CyDesigner.Common.Db.DeviceDb.Catalog.CyDcPlugin.PostPluginsLoadedInit()

   at CyDesigner.Framework.CyPlugin.InitializePlugins(IEnumerable`1 plugins)

   at CyDesigner.Common.ProjMgmt.PrjMgrTool.CyPrjMgrTool.LoadPlugins()

   at CyDesigner.Common.ProjMgmt.PrjMgrTool.CyPrjMgrTool.Run(CyApp app, CyErr& err)

   at CyDesigner.Common.ProjMgmt.PrjMgrTool.CyPrjMgrTool.Main(String[] args)

The full Jenkins output is shown below. Has anyone else had luck with this?

Started by user anonymous

Building in workspace C:\Program Files (x86)\Jenkins\workspace\Switchbox_psoc

[Switchbox_psoc] $ cmd /c call C:\Windows\TEMP\hudson5210422228259853648.bat

C:\Program Files (x86)\Jenkins\workspace\Switchbox_psoc>cd PSoC\Switchbox

C:\Program Files (x86)\Jenkins\workspace\Switchbox_psoc\PSoC\Switchbox>dir

Volume in drive C has no label.

Volume Serial Number is 747E-8C27

Directory of C:\Program Files (x86)\Jenkins\workspace\Switchbox_psoc\PSoC\Switchbox

01/12/2018 01:51 PM <DIR> .

01/12/2018 01:51 PM <DIR> ..

01/12/2018 02:38 PM <DIR> Switchbox.cydsn

01/12/2018 01:51 PM 1,265 Switchbox.cywrk

  1 File(s) 1,265 bytes

  3 Dir(s) 43,292,274,688 bytes free

C:\Program Files (x86)\Jenkins\workspace\Switchbox_psoc\PSoC\Switchbox>"c:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\bin\cyprjmgr.exe" -w "C:\Program Files (x86)\Jenkins\workspace\Switchbox_psoc\PSoC\Switchbox\Switchbox.cywrk"

Error: mgr.M0027: Argument passed in is not serializable.

Parameter name: value (App=cyprjmgr)

  at System.Collections.ListDictionaryInternal.Add(Object key, Object value)

  at CyDesigner.Common.Base.CyRsltOrErr`1.get_Value()

  at CyDesigner.Common.Db.DeviceDb.Catalog.CyWcdMgr.get_InstallBaseDir()

  at CyDesigner.Common.Db.DeviceDb.Catalog.CyDcPlugin.get_DeviceDataPath()

  at CyDesigner.Common.Db.DeviceDb.Catalog.CyDcPlugin.PostPluginsLoadedInit()

  at CyDesigner.Framework.CyPlugin.InitializePlugins(IEnumerable`1 plugins)

  at CyDesigner.Common.ProjMgmt.PrjMgrTool.CyPrjMgrTool.LoadPlugins()

  at CyDesigner.Common.ProjMgmt.PrjMgrTool.CyPrjMgrTool.Run(CyApp app, CyErr& err)

  at CyDesigner.Common.ProjMgmt.PrjMgrTool.CyPrjMgrTool.Main(String[] args)

cyprjmgr [-h] [-ver] [-wrk <workspace_name>] [-clean] [-build] [-rebuild]

[-archive <archive_level> <archive_as_zip>] [-t <toolchain>] [-c <config>]

[-p <TopProject>] [-n <TopDesign>] [-d <selectedDev>]

[-m <paramsFile>] [-import <Source_Project> <Source_Component>]

[-rename <component_name> <new_name>] [-delete <component_name>]

[-exclude <component_name>] [-l <NewPrjName>]

[-s] [-v <visibility>] [-prj <Target_Project>] [-cmp <Target_Component>]

[-addprj <prj_path>] [-cp <path>] [-con <Target_Project>] [-batch <file_name>]

[-updateComp <source_project> <source_component>] [-updatePrj <source_project>]

[-updateInst] [-updateDWInst] [-forceWrite] [-noCustBuild] [-noRefresh]

[-ol <compiler optimization level>] [-warn <High|Low|None>]

[-buildPreCompCust <Project>] [-updateInstIfNeeded]

[-ignoreDepsWarning] [-allowIllegalUpdates] [-export <IDE>] [-pdlPath <path>]

The following options are tool wide:

  -h Displays this help message

  -ver Displays the version and build number of cyprjmgr

The following options apply to the chosen workspace:

  -wrk, -w Specifies the workspace to be used

  -prj Specifies the target project on which all the command line

  options will be targeted. In case target project is not

  specified, Top Project of the workspace becomes the target

  project

  -p Sets the Top Project in the workspace

  -cmp, -o Specifies the target component on which all the library options

  will be targeted. In case target component is not specified,

  the Top Block of the Target Project becomes the Target Component

  -addprj Adds an existing project <prj_path> to the workspace

  -l Adds a new empty library project with name <NewPrjName> to the

  workspace

  -d Sets the selected device of projects to be built

  -cp Copies the entire workspace to the location specified by

  <path>, all command line options will act on the copy created

The following four options target the entire workspace unless the

target project is set with -prj:

  -clean Cleans the workspace/project

  -build Builds the workspace/project

  -rebuild Rebuilds the workspace/project

  -archive Archives the workspace/project with different archiver levels

  (complete/typical), and as zip or nozip

The following options apply to the target project:

  -t Sets the tool chain the action should use (Keil, ARM etc.)

  -c Sets configuration the action should use (Debug, Release)

  -ol Sets compiler optimization level

  -warn Sets compiler warning level

  -n Sets the Top Design of the Top Project

  -m Parameters file that will override the default parameter values

  of the schematic in the TopDesign of the Top Project

  -import Imports the Source Component from the Source Project into the 

  target project of the workspace

  -rename Renames component_name in target project of the workspace to 

  new_name

  -delete Deletes component from the disc

  -exclude Excludes component from the target project of the workspace

  -s Lists the external dependencies of the target project

  -v Sets the visibility of the target component to true/false

  -con Checks the consistency of the target project of the workspace

  -batch Reads a file containing a series of commands, one on each line.

  Executes the commands one by one. When batch option is used, all

  other optional switches are ignored

-updateComp Updates a component in the Target Project from the source project

-updatePrj Updates the Target Project from the Source Project

-updateInst Updates the instances on the schematic with the latest components

-forceWrite Makes read-only files writable and then makes the change

-noCustBuild Delay building of customizer DLLs until the end (e.g., during

  imports)

-noRefresh Disable updates from the refresh manager (Use with extreme care)

-buildPreCompCust Build customizer for a project

-updateDWInst Updates the design-wide instances with the latest components

-updateInstIfNeeded Update instances to minimum valid version

-ignoreDepsWarning Suppress SystemDepNotFoundOnDisk warning while building

  primitives

-allowIllegalUpdates Allows updating instances to latest version, even if illegal

  -export Exports the project to the target IDE. Valid targets are EWA, Eclipse and uVision

-generateDescFiles For all specified projects that have 'Generate description files'

  enabled, generates the description files.

-verifyDescFileEnabled Verifies that all specified projects have 'Generate description files' enabled.

-verifyDescFileContents Verifies that all specified projects (that have 'Generate description

  files' enabled) have generated files that are in-sync with the current

  version of their source files.

  -pdlPath Sets the path to the PDL file for the project

C:\Program Files (x86)\Jenkins\workspace\Switchbox_psoc\PSoC\Switchbox>exit 6

Build step 'Execute Windows batch command' marked build as failure

Finished: FAILURE

hello everyone.

                     anyone please give  me one verilog example project in psoc by creating verilog component.