PSoC™ Creator & Designer Forum Discussions
I’m having a problem trying to compile the CE222221, PSoC 6 MCU Voice Recorder, example program that is referenced in the CY8CKIT-062-WiFi-BT, PSoC 6 WiFi-BT Pioneer Kit Guide. Following the instructions in both the guide and the CE222221 app note, the compile fails due to missing header files. I’m using the latest example download, CY8CKIT-062-WiFi-BT_PSoC®6_WiFi-BT_Pioneer_Kit_Code_Examples.zip, from Cypress’ website. The app note mentions a FreeRTOSConfig.h header file and states “DO NOT replace the FreeRTOSConfig.h file”. The example zip includes the header file, but when I try to compile I get the following message:
“The following configuration files have been removed from the project because they are no longer used by the design. These files are still on disk but changes made to them will need to be replicated in the new files. Removed files: C:\Users\gordonmx\Documents\PSoC Creator\4.2\Examples\PSoC 6 MCU\CE222221_Voice_Recorder.cydsn\FreeRTOSConfig.h
Some configuration files are no longer used by the design. These files have been removed from the project with new files added in their place. Any changes made to the files in question will need to be replicated in the newly added files.”
Note: Because my PC is running Windows 7 Pro and the default directory for the examples is in the “C:\Program files” path with restricted permissions, I set up my workspace into C:\Users\gordonmx\Documents\PSoC Creator\4.2\Examples\PSoC 6 MCU\CE222221_Voice_Recorder.cydsn
When I press [OK] the build continues, but fails with the following message:
In file included from main_cm4.c:43:0:
The command 'arm-none-eabi-gcc.exe' failed with exit code '1'.
- rtos.h:46:26: fatal error: FreeRTOS.h: No such file or directory
--------------- Build Failed: 12/05/2018 14:55:21 ---------------
The header file rtos.h does exist, but FreeRTOS.h does not, as well a number of other header files referenced in rtos.h, such as task.h, queue.h, semphr.h and event_groups.h.
Cypress Product Version (from PCreator About Page)-
PSoC Creator 4.2 (22.214.171.1241)
Culture: English (United States)
OS Version: Microsoft Windows NT 6.1.7601 Service Pack 1
CLR Version: 4.0.30319.42000
Installed CyInstaller Products:
CY8CKIT-042-BLE Kit 1.0 Rev.*G
CY8CKIT-042-BLE-A Kit 1.0 Rev.*B
CY8CKIT-044 PSoC 4 M-Series Pioneer Kit 1.0 Rev.*B
CY8CKIT-048 PSoC Analog Coprocessor Pioneer Kit 1.0 Rev.**
CY8CKIT-062-WiFi-BT PSoC 6 WiFi-BT Pioneer Kit 1.0 Rev.**
Cypress Document Manager 1.0 SP1
Peripheral Driver Library 3.0.4
PSoC Programmer 3.27.3
PSoC Creator 4.2
I’ve attached the build.log for more details. What am I doing wrong? Thank you for your assistance.
Gordon MargulieuxShow Less
this is a UDB implementation of a 16-bit fixed point CORDIC for calculating the sine and cosine of a given angle. It is supported on PSoC 3 and can possibly (ignoring warnings) run up to 33 MHz. I've attached a demo project with the project library so try running it on the CY8CKIT-001 Devkit.Show Less
I am a software engineer in Shenzhen.
I am designing a product that uses the CY8CKIT-033A development board.
We have implemented the product features and are in mass production.
Now Apple upgrades the Authentication Coprocessor 2.0C to 3.0.
And from next year, 2.0C will no longer be available.
But, thhe iAP2 component do not support Apple Authentication 3.0 Coprocessor.
So, can you help me solve this problem?
Shide LuShow Less
So the image is my top design, I'm using PSOC creator 4.2 and play around with CY8CKIT-059 kit. I want to have the PWM output at pin 1.7. However if I only wire the output of the SR flip-flop to pin 1.7 or any pins from port 1 it will not have any output after counter is started. Chain a dummy output pin from port 3 seems allow the pin 1.7 to output, but now I have another output which I don't really want. I think this is not an intended behavuour and there should be a bug causing this, but I'm not sure where the bug is. Right now I just have to deal with a unintended output. Any ideas and suggestions would be helpful. Thanks!
Its been a long time since I have used the SPIM block and associated commands.
I have a thermocouple that goes to the MAX31855 board. It uses SPI to communicate. When SS goes low it sends its 32 bits of data. I am only interested in bits 14-31.
I forget the correct way to clear the rx buffer, read rx data and then what to do with said data. Attached is the project I have so far. Also I am novice when it comes to C code so if I have int8s or unit 32_t's im not even sure what they do all that well. Thanks for your help in this.Show Less
This post attempts to address five questions that arose during the creation of an asynchronous interface in PSoC.
Random errors were eliminated by changing parameters without a clear explanation provided.
To those reading this, please add any references, links or comments that will help designers understand the details of asynchronous systems, how to minimize the chance for errors to propagate and build robust designs using minimal resources using PSoC components.
An RS485 interface was created in two PSoC 5 based systems, one as Master, the other Slave:
UART: 115200 baud, 1 start, 1 stop bit, UART Rx pin configured in “double-sync” mode.
System clock: 30 MHz
IDE: PSoC Creator 4.1
UART: 115200 baud, 1 start, 1 stop bit, UART Rx pin configured in “transparent” mode
System clock: 4 MHz
IDE: PSoC Creator 4.1
When using the 4-byte HW FIFO configuration with the “Internal Interrupt” on the RS485 Slave board, there were occasional missed bytes on the Slave receiver and the UART would show overrun flag active. The issue went away with any one of the following three changes to the Slave board’s configuration:
1. Changed the Slave UART Rx pin to double sync.
a) Why is double-sync required of external pins when connected to a UART? When the UART is connected internally, there is no double-sync setting.
b) When should double-sync be used?
2. Maintained transparent Rx Pin mode and changed to a 5-byte FIFO that implements a SW-based buffer and an “External Interrupt”.
c) What is the difference between these two FIFO designs and why does one work better than the other?
3. Maintained transparent Rx Pin mode and increased the System Clock to 12MHz.
d) Why does a faster system clock affect this outcome?
For all tests, the Master transmitter is sending bytes at 115200 baud using the PSoC RS485 library functions, and with the oscilloscope they can see there isn’t any inter-byte delay applied to the TX frame.
e) Is there any inter-byte delay recommended (or not recommended) for this library?
The following thoughts are intended to help address the five questions above:
A) Double sync filters out noise and prevents metastable states by clocking external signals through buffer registers so their value as presented to internal PSoC logic changes only on PSoC System clock boundaries. This is opposite of “Transparent” mode that implies the passing of raw asynchronous external signals directly to internal logic.
B) Double sync should be used when signals switching near the rate of asynchronous clocks are shared between systems. Note that UART signals are typically switching at a rate much slower than the system clock. Double syncing adds integrity to signals at the expense of a slight delay and use of resources – a couple registers.
C) Three changes are noted here: Increasing FIFO over 4-bytes, SW based buffers and External interrupts
- Increasing the FIFO over 4-bytes utilizes interrupts that changes the dynamics of the UART implementation – reference “RX Buffer Size” on page 10 of the UART component data sheet @ http://www.cypress.com/documentation/component-datasheets/universal-asynchronous-receiver-transmitter-uart.
- SW based buffers will be slower than hardware buffers. All data into a software buffer will be synchronized with the system clock, which dictates the cadence that software commands are performed.
- External interrupts will by definition be slower. Internal interrupts could induce race conditions in cases where the interrupt is triggered before a process is complete. Interrupt handling should be analyzed at a system level to allow critical processes to complete in a timely fashion.
D) System clock timing issues are described as %ERR – reference %ERR calculation in UART Component Datasheet rev D page 50 @ http://www.cypress.com/documentation/component-datasheets/universal-asynchronous-receiver-transmitter-uart
E) I am not aware of any general inter-byte delay recommended. The implementation should be analyzed to ensure buffer space is available before data is transmitted.
Some additional information may be found in related posts on Cypress Community:
Problem with changing PSoC CPU clock @ https://community.cypress.com/message/147645#147645
PSoC5LP UART receiver with a RX buffer > 4 bytes @ https://community.cypress.com/message/100334#100334Show Less
I tried to update from PSoC Creator 4.0 to 4.1 today. The update stalled. There was no error message or window, just this sitting in my taskbar:
I then tried to uninstall everything and install 4.2 from scratch. That installation stalled in the same spot.
I have gone through: Troubleshooting PSoC® Creator™ Issues - KBA217546
but have not been able to find a solution.
When I run C:\Program Files (x86)\Cypress\PSoC Creator\4.2\Updater\PSoCCreatorInstaller.exe, I get an unhandled exception stating, "The given key was not present in the dictionary"
Any ideas?Show Less
Is there a fundamental reason why the PDM to PCM component is not available on the PSoC 5LP, only on PSoC 6?Show Less
Hi we just noticed that the KitProg programmer is drawing 25ma from our PCBs that is using the PSoC 4000S chip. Isn't the KitProg supposed to draw 0ma or a negligible amount of current from a board? ThanksShow Less
I am trying to get code that turns a LED on in Psoc Creator to work but I'm getting the following errors on the bottom image. I checked the configuration of the LED and don't think that's the cause of the issue. Any suggestions?