Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

PSoC™ Creator & Designer Forum Discussions

ETRO_SSN583
Level 9
Level 9
100 sign-ins 5 likes given 1000 replies posted

Is there anyway of overriding the WaveDAC8 clock limit ? It would be nice

if that limit was a warning rather than a hard limit.

As a workaround I am going to use DMA and a DAC and a table to get the analysis done, but

a mod to that component would be nice.

Regards, Dana.

0 Likes
1 Solution
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Dana,

I haven't try this trick with WaveDAC8, but oftentimes a component clock speed limitation can be bypassed by adding an extra component (NOT, or NOT-NOT, etc) in front of the clock input. The Customizer won't be able to read the clock frequency (it can extract only real clocks settings), and will ignore the issue altogether. Alternatively, one can use the Dummy component, which can serve the same purpose of fooling the customizer when placed between the clock and clock input terminal

The Dummy: empty component for digital bus routing

For example, using this technique, the PSoC5 ADC_SAR can be overclocked up to 1.88 Ms/sec.

/odissey1

View solution in original post

0 Likes
3 Replies
Len_CONSULTRON
Level 9
Level 9
500 solutions authored 1000 replies posted 750 replies posted

Dana,

There are two ways to get around this issue.

  1. External Clock solution.
    1. Assign an external clock of 1MHz (max allowed) to WaveDAC8. This will satisfy the component's creation testing limits.
    2. Let the TopDesign build ("Generate Application" phase) without error.
    3. Modify the divider of the clock you used for the external clock.  There are APIs calls to lower the divider which will increase the input frequencies.
  2. Use the VDAC8 component with an external Strobe input and your desired external clock input.  In this solution you and create your own WaveDAC8 equivalent. 

Having given you two solutions I have to note there are practical reasons why there are 1MHz clocking limitations for the WaveDAC8 component.  The "Generate Application" phase performs a "Static timing analysis...".   In this sub-phase, the known timing limitations are tested for setup and hold timing violation to clocked latches.  

The warning/errors provided by the WaveDAC8 component is to warn the designer in advance that clocking frequencies above 1MHz could provide a static timing analysis.   The reality is the 1MHz limitation is based on worst-case UDB block, datapath and analog path routing delays across the entire rated operating temperature range.  The timing analysis also covers manufacturing process variations.

You can improve these worst-case timing by manually routing datapath and analog routing to optimize it.  Also limiting the operational temperature range for your application to room temp +/- 10C would be helpful.

Len

Len
"Engineering is an Art. The Art of Compromise."
0 Likes
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Dana,

I gave up WaveDAC8 due to many issues long time ago and use own component (WaveGen8). You may find a project using WaveGen8, for example, here (the component is included into the project):

ADC_SAR - Filter - VDAC streaming demo using DMA

All it does is transferring data from RAM to various targets, e.g. VDAC. The sine function is built-in, but any arbitrary data can be written into the buffer.

/odissey1

SAR-Filter-VDAC_signed_FIFO_02a_WaveGen.png

0 Likes
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Dana,

I haven't try this trick with WaveDAC8, but oftentimes a component clock speed limitation can be bypassed by adding an extra component (NOT, or NOT-NOT, etc) in front of the clock input. The Customizer won't be able to read the clock frequency (it can extract only real clocks settings), and will ignore the issue altogether. Alternatively, one can use the Dummy component, which can serve the same purpose of fooling the customizer when placed between the clock and clock input terminal

The Dummy: empty component for digital bus routing

For example, using this technique, the PSoC5 ADC_SAR can be overclocked up to 1.88 Ms/sec.

/odissey1

0 Likes