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PSoC™ Creator & Designer Forum Discussions

RiTa_288331
Level 2
10 replies posted 10 questions asked 5 replies posted
Level 2

Greetings all!  Using the PSOC 5LP kit (CY8CKIT-059), I have some questions on the ADC conversion/sampling rates.

   

My goal is to have 3 ADC inputs that simultaneously sample, without using the sample-hold component.
In order to do that, the 5LP kit does have 2 SAR ADCs and 1 DelSig ADC, so I do have enough ADCs to do this.

   

To trigger the ADCs, I am using one timer component with an output of 100kHz, so I think I will get a 100kHz sampling rate (this timer is connected to the SOC pin of each ADC - this way, I can get simultaneous samples).

   

1. I think I want Single Sample conversion mode - is this true?

   

2. Why do I have to specify the conversion rate when I double click on each ADC block?  
By virtue of the fact that I am using a 100kHz timer at the SOC pin, doesn't this mean that the conversion
rate is 100kHz?  I don't understand how the two numbers (external timer frequency vs. internal conversion rate)
could be different.
 

   

If this helps, I have included a picture to show what I'm trying to do.

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HeLi_263931
Level 8
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Level 8

The actual conversion speed (and thefore the conversion rate) of the ADCs depends on the clock they are driven with. So to really get the 100ksps you want the ADCs should convert faster than that. You SOC signal derived from the 100kHz clock is just signalling _when_ the conversion should start. E.g. the SAR ADC with 12 bits converts at 111ksps with a 2MHz clock, but the DelSig ADC in 8bit mode converts at 74ksps with a 6MHz clock.

   

Yes, you want single sample mode. All other modes are free-running and take one sample after each other. Note that the DelSig ADC can handle only up to 75ksps in that mode. Continuous mode is faster, but won't stop and wait for SOC.

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HeLi_263931
Level 8
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Level 8

The actual conversion speed (and thefore the conversion rate) of the ADCs depends on the clock they are driven with. So to really get the 100ksps you want the ADCs should convert faster than that. You SOC signal derived from the 100kHz clock is just signalling _when_ the conversion should start. E.g. the SAR ADC with 12 bits converts at 111ksps with a 2MHz clock, but the DelSig ADC in 8bit mode converts at 74ksps with a 6MHz clock.

   

Yes, you want single sample mode. All other modes are free-running and take one sample after each other. Note that the DelSig ADC can handle only up to 75ksps in that mode. Continuous mode is faster, but won't stop and wait for SOC.

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odissey1
Level 9
First comment on KBA 1000 replies posted 750 replies posted
Level 9
        Check examples posted in this thread, which has both ADC_SAR, DelSig_ADC and sample-and-hold demos http://www.cypress.com/comment/381696#comment-381696 PS. What is the reason you try to avoid using sample-and-hold component?   
RiTa_288331
Level 2
10 replies posted 10 questions asked 5 replies posted
Level 2

Thank you both for your responses!

   

I'm trying to use three separate ADCs because:

   

1. Speed - if I use one ADC and a sample/hold, then I have to wait for three sequential ADC conversions.  I'm trying to run three "parallel" ADCs to speed the process up (this gives me more time between ADC samplings to do number crunching/processing).

   

2. Learning/didactic example: I'm trying to use both the SAR and DelSig ADCs to better understand them, and their differences.

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HeLi_263931
Level 8
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Level 8

The SAR ADC can run with 1Msps, and for scanning 3 channels you only need 300ksps, so its more than fast enough. Using the Sequencing SAR ADC also frees you from handling the channels, you just get notified when all channels are converted and can read the values.