UDB Editor question: If I load a FIFO (eg. F0) register of a 32-bit DataPath using DMA, will it give me 1 or 2 "FIFO Not Empty" signals?

[Len_CONSULTRON]

I have a very advanced question about the use of FIFO registers in 32-bit datapaths.  

I'm using the UDB Editor and I've constructed a component with a 32-bit datapath.

I realize that the UDB blocks and datapaths are at most 16-bits PHUB wide.  When I try to DMA directly into ANY of the datapath registers (A0, A1, D0, D1, F0 or F1) I have to break up the DMA into two 16-bit TDs otherwise it would fail. (Note: A CPU write can be done as a 32-bit write. However it is probably two 16-bit writes internally.)

Currently my component application is writing into the F0 register with the CPU and I get one "F0 block status (empty)" signal.  This is good.  I use this F0 status signal to launch a state-machine.  The state-machine logic is counting on ALL 32-bits being loaded in F0 before executing.

Since it appears I cannot DMA as a single 32-bit TD into F0 but have to break it up into two 16-bit TDs, my question is:  Will I get two "F0 block status (empty)" signals?  One signal on the load of the LSW and the other on the load of the MSW?

[RodolfoGL]

Actually you would get 4 F0 block status for a 32-bit datapath, In your case, you want to AND all these 4 signals. Or you can only use one of them, specifically the one linked to the FIFO that is written the last.

[Len_CONSULTRON]

Rodolfo,

Actual configuring a 32-bit datapath, I only get one F0 block status event on one CPU write to F0.  (It appears all the F0 block statuses from each UDB block are ANDd together.)  

The issue I'm inquiring about is since I have to break up DMA writes into TWO 16-bit accesses to F0, do I get two F0 status event signals?  One for the first 16-bits and the second for the second 16-bits?

[RodolfoGL]

Len, 

If using a 32-bit datapath, the f0_blk_stat has to be a 4-bit wire signal. 

So you should so something like this:

wire [3:0] f0_blk_stat;

...
.f0_blk_stat( f0_blk_stat ), 
...

If you do like this:

wire f0_blk_stat;

...
.f0_blk_stat( f0_blk_stat ), 
...

the routing will link to a single F0 status (not sure which one). This might work if it is linked to the F0 that the DMA writes the last.

[Len_CONSULTRON]

Rodolfo,

I can't tell you if this is already taken care of in the Verilog output of the UDB_Editor compilation.  Or if I am only looking at f0_blk_stat from only one datapath block.  

When using the CPU to load the F0 register, I'm only getting one event.

[RodolfoGL]

When you say one datapath block, is it a 32-bit datapath?

Again, f0_blk_stat is a 4 wire signal for a 32-bit datapath. When writing to the F0 register, you should see all these four signals going high. I suspect you will see a small delay between the first two and the last two, since you write in bursts of 16-bits.

You can scope all the four signals to confirm that:

wire [3:0] f0_blk_stat;

...
.f0_blk_stat( f0_blk_stat ), 
...

assign debug1 = f0_blk_stat[0];
assign debug2 = f0_blk_stat[1];
assign debug3 = f0_blk_stat[2];
assign debug4 = f0_blk_stat[3];

Where the debug wires are connected directly to pins, so you can scope them.

[Len_CONSULTRON]

Rodolfo,

It is assigned as a 32-bit datapath.

Here's the Verilog output:

/*******************************************************************************
* Description:
*  Verilog implementation autogenerated from DCmp_thresh2_32b_v1_1.cyudb at 04/08/2022 07:31:59.
*
* Note:
*  This module definition will automatically be incorporated during the "HDL Generation"
*  phase of a design which uses this UDB document. 
*  Alternatively, the contents of this pane may be copied and used as a starting point
*  for a verilog component implementation. The Datapath Configuration Tool may be used
*  to adjust advanced datapath parameters (accessible from the Tools menu).
*  For more details, see the Component Author Guide and Technical Reference Manuals.
*  Both can be accessed by selecting Help -> Documentation.
*******************************************************************************/

`include "cypress.v"
/* ==================== Include Component Definitions ==================== */

module DCmp_thresh2_32b_v1_1 (
    input wire clock, 
    input wire two_inp, 
    input wire sign_en, 
    output wire EQ1, 
    output wire LT1, 
    output wire TSIGN, 
    output wire EQ2, 
    output wire LT2, 
    output wire F0NE
);

/* ==================== Wire and Register Declarations ==================== */
localparam [1:0] new_thresh = 2'b01;
localparam [1:0] no_new_thresh = 2'b00;
reg sign_r;
wire d_EQ_T1;
wire d_LT_T1;
wire d_EQ_T2;
wire d_LT_T2;
wire sign_bit;
wire f0_empty;
wire DCMP_dp_d0_load;
wire DCMP_dp_d1_load;
wire DCMP_dp_f0_load;
wire DCMP_dp_f1_load;
wire DCMP_dp_route_si;
wire DCMP_dp_route_ci;
wire  [2:0] DCMP_dp_select;
reg calc_sign;
reg  [1:0] SM_1;

/* ==================== Assignment of Combinatorial Variables ==================== */
assign EQ1 = (d_EQ_T1);
assign LT1 = (d_LT_T1);
assign TSIGN = (sign_r);
assign EQ2 = (d_EQ_T2);
assign LT2 = (d_LT_T2);
assign F0NE = (!f0_empty);
assign DCMP_dp_d0_load = (!f0_empty);
assign DCMP_dp_d1_load = (1'b0);
assign DCMP_dp_f0_load = (1'b0);
assign DCMP_dp_f1_load = (1'b0);
assign DCMP_dp_route_si = (1'b0);
assign DCMP_dp_route_ci = (1'b0);
assign DCMP_dp_select[0] = (two_inp);
assign DCMP_dp_select[1] = (calc_sign);
assign DCMP_dp_select[2] = (1'b0);

/* ==================== Assignment of Registered Variables ==================== */
always @ (posedge clock)
begin : register_assignments
    sign_r <= ((calc_sign ? sign_bit : sign_r));
end

/* ==================== DCMP_dp (Width: 32) Instantiation ==================== */
parameter DCMP_dp_dpconfig0 = 
{
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM0: Compare to one input */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_A1, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGB,  /*CFGRAM1: Compare to two inputs */
    `CS_ALU_OP__AND, `CS_SRCA_A1, `CS_SRCB_D0, `CS_SHFT_OP___SL, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGB,  /*CFGRAM2: Determine sign bit */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM3:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM4:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM5:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM6:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM7:  */
    8'hFF, 8'h00, /* CFG9 */
    8'hFF, 8'hFF, /* CFG11-10 */
    `SC_CMPB_A1_D1, `SC_CMPA_A0_D1, `SC_CI_B_ARITH, `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL, `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN, `SC_SI_A_DEFSI, /* CFG13-12 */
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0, `SC_SR_SRC_REG, `SC_FIFO1_BUS, `SC_FIFO0_BUS, `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN, `SC_FB_NOCHN, `SC_CMP1_NOCHN, `SC_CMP0_NOCHN, /* CFG15-14 */
    3'b000, `SC_FIFO_SYNC__ADD, 2'b000, `SC_FIFO1_DYN_OF, `SC_FIFO0_DYN_OF, `SC_FIFO_CLK1_POS, `SC_FIFO_CLK0_POS, `SC_FIFO_CLK_BUS, `SC_FIFO_CAP_AX, `SC_FIFO__EDGE, `SC_FIFO__SYNC, `SC_EXTCRC_DSBL, `SC_WRK16CAT_DSBL /* CFG17-16 */
};
parameter DCMP_dp_dpconfig1 = 
{
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM0: Compare to one input */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_A1, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGB,  /*CFGRAM1: Compare to two inputs */
    `CS_ALU_OP__AND, `CS_SRCA_A1, `CS_SRCB_D0, `CS_SHFT_OP___SL, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGB,  /*CFGRAM2: Determine sign bit */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM3:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM4:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM5:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM6:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM7:  */
    8'h00, 8'h00, /* CFG9 */
    8'h00, 8'h00, /* CFG11-10 */
    `SC_CMPB_A1_D1, `SC_CMPA_A0_D1, `SC_CI_B_CHAIN, `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL, `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN, `SC_SI_A_CHAIN, /* CFG13-12 */
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0, `SC_SR_SRC_REG, `SC_FIFO1_BUS, `SC_FIFO0_BUS, `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED, `SC_FB_CHNED, `SC_CMP1_CHNED, `SC_CMP0_CHNED, /* CFG15-14 */
    3'b000, `SC_FIFO_SYNC__ADD, 2'b000, `SC_FIFO1_DYN_OF, `SC_FIFO0_DYN_OF, `SC_FIFO_CLK1_POS, `SC_FIFO_CLK0_POS, `SC_FIFO_CLK_BUS, `SC_FIFO_CAP_AX, `SC_FIFO__EDGE, `SC_FIFO__SYNC, `SC_EXTCRC_DSBL, `SC_WRK16CAT_DSBL /* CFG17-16 */
};
parameter DCMP_dp_dpconfig2 = 
{
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM0: Compare to one input */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_A1, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGB,  /*CFGRAM1: Compare to two inputs */
    `CS_ALU_OP__AND, `CS_SRCA_A1, `CS_SRCB_D0, `CS_SHFT_OP___SL, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGB,  /*CFGRAM2: Determine sign bit */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM3:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM4:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM5:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM6:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM7:  */
    8'h00, 8'h00, /* CFG9 */
    8'h00, 8'h00, /* CFG11-10 */
    `SC_CMPB_A1_D1, `SC_CMPA_A0_D1, `SC_CI_B_CHAIN, `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL, `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_CHAIN, `SC_SI_A_CHAIN, /* CFG13-12 */
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0, `SC_SR_SRC_REG, `SC_FIFO1_BUS, `SC_FIFO0_BUS, `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED, `SC_FB_CHNED, `SC_CMP1_CHNED, `SC_CMP0_CHNED, /* CFG15-14 */
    3'b000, `SC_FIFO_SYNC__ADD, 2'b000, `SC_FIFO1_DYN_OF, `SC_FIFO0_DYN_OF, `SC_FIFO_CLK1_POS, `SC_FIFO_CLK0_POS, `SC_FIFO_CLK_BUS, `SC_FIFO_CAP_AX, `SC_FIFO__EDGE, `SC_FIFO__SYNC, `SC_EXTCRC_DSBL, `SC_WRK16CAT_DSBL /* CFG17-16 */
};
parameter DCMP_dp_dpconfig3 = 
{
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM0: Compare to one input */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_A1, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGB,  /*CFGRAM1: Compare to two inputs */
    `CS_ALU_OP__AND, `CS_SRCA_A1, `CS_SRCB_D0, `CS_SHFT_OP___SL, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGB,  /*CFGRAM2: Determine sign bit */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM3:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM4:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM5:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM6:  */
    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA,  /*CFGRAM7:  */
    8'h00, 8'h00, /* CFG9 */
    8'h00, 8'h00, /* CFG11-10 */
    `SC_CMPB_A1_D1, `SC_CMPA_A0_D1, `SC_CI_B_CHAIN, `SC_CI_A_CHAIN, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL, `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI, `SC_SI_A_CHAIN, /* CFG13-12 */
    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0, `SC_SR_SRC_REG, `SC_FIFO1_BUS, `SC_FIFO0_BUS, `SC_MSB_ENBL, `SC_MSB_BIT7, `SC_MSB_CHNED, `SC_FB_CHNED, `SC_CMP1_CHNED, `SC_CMP0_CHNED, /* CFG15-14 */
    3'b000, `SC_FIFO_SYNC__ADD, 2'b000, `SC_FIFO1_DYN_OF, `SC_FIFO0_DYN_OF, `SC_FIFO_CLK1_POS, `SC_FIFO_CLK0_POS, `SC_FIFO_CLK_BUS, `SC_FIFO_CAP_AX, `SC_FIFO__EDGE, `SC_FIFO__SYNC, `SC_EXTCRC_DSBL, `SC_WRK16CAT_DSBL /* CFG17-16 */
};
cy_psoc3_dp32 #(
    .cy_dpconfig_a( DCMP_dp_dpconfig0 ), .cy_dpconfig_b( DCMP_dp_dpconfig1 ), .cy_dpconfig_c( DCMP_dp_dpconfig2 ), .cy_dpconfig_d( DCMP_dp_dpconfig3 ),
    .d0_init_a( 8'b00000000 ), .d0_init_b( 8'b00000000 ), .d0_init_c( 8'b00000000 ), .d0_init_d( 8'b00000000 ),
    .d1_init_a( 8'b00000000 ), .d1_init_b( 8'b10000000 ), .d1_init_c( 8'b00000000 ), .d1_init_d( 8'b00000000 ),
    .a0_init_a( 8'b00000000 ), .a0_init_b( 8'b00000000 ), .a0_init_c( 8'b00000000 ), .a0_init_d( 8'b00000000 ),
    .a1_init_a( 8'b00000000 ), .a1_init_b( 8'b10000000 ), .a1_init_c( 8'b00000000 ), .a1_init_d( 8'b00000000 ))
    DCMP_dp(
        .clk( clock ),
        .cs_addr( DCMP_dp_select ),
        .route_si( DCMP_dp_route_si ),
        .route_ci( DCMP_dp_route_ci ),
        .f0_load( DCMP_dp_f0_load ),
        .f1_load( DCMP_dp_f1_load ),
        .d0_load( DCMP_dp_d0_load ),
        .d1_load( DCMP_dp_d1_load ),
        .ce0( { d_EQ_T1, DCMP_dp_ce0_3, DCMP_dp_ce0_2, DCMP_dp_ce0_1 } ), 
        .cl0( { d_LT_T1, DCMP_dp_cl0_3, DCMP_dp_cl0_2, DCMP_dp_cl0_1 } ), 
        .z0(  ), 
        .ff0(  ), 
        .ce1( { d_EQ_T2, DCMP_dp_ce1_3, DCMP_dp_ce1_2, DCMP_dp_ce1_1 } ), 
        .cl1( { d_LT_T2, DCMP_dp_cl1_3, DCMP_dp_cl1_2, DCMP_dp_cl1_1 } ), 
        .z1(  ), 
        .ff1(  ), 
        .ov_msb(  ), 
        .co_msb(  ), 
        .cmsb(  ), 
        .so( { sign_bit, DCMP_dp_so_3, DCMP_dp_so_2, DCMP_dp_so_1 } ), 
        .f0_bus_stat(  ), 
        .f0_blk_stat( { f0_empty, DCMP_dp_f0_blk_stat_3, DCMP_dp_f0_blk_stat_2, DCMP_dp_f0_blk_stat_1 } ), 
        .f1_bus_stat(  ), 
        .f1_blk_stat(  )
    );

/* ==================== State Machine: SM_1 ==================== */
always @ (posedge clock)
begin : no_new_thresh_state_logic
    case(SM_1)
        no_new_thresh : 
        begin
            calc_sign <= (0);
            if (( !f0_empty & sign_en ) == 1'b1)
            begin
                SM_1 <= new_thresh ;
            end
        end
        new_thresh : 
        begin
            calc_sign <= (1);
            if (( 1'b1 ) == 1'b1)
            begin
                SM_1 <= no_new_thresh ;
            end
        end
        default :
        begin
            SM_1 <= no_new_thresh;
        end
    endcase
end

endmodule

I don't "peek under the cover" to view this output very often since I'm not so familiar with Verilog syntax.

I did notice on this 32-bit implementation that there is this line:

.f0_blk_stat( { f0_empty, DCMP_dp_f0_blk_stat_3, DCMP_dp_f0_blk_stat_2, DCMP_dp_f0_blk_stat_1 } ),

I'm assuming this is a function to combine DCMP_dp_f0_blk_stat_3, DCMP_dp_f0_blk_stat_2, DCMP_dp_f0_blk_stat_1 and DCMP_dp_f0_blk_stat_0 to create the logic output f0_empty.   Is this assignment a wired 'AND' or and 'OR'?

 DCMP_dp_f0_blk_stat_'x' must be the default names for each of the f0_blk_stat bits in the 32-bit datapath.

If it creates a wired 'AND' then two 16-bit writes won't invoke the f0_empty signal.  If it's a wired 'OR', then I would get two f0_empty signals on two 16-bit writes and 4 signals on 4 8-bit writes.

[RodolfoGL]

As I mentioned, the f0_blk_stat is a 4 wire signal, as shown in the Verilog code. It seems the UDB Editor only let you pick the first signal (f0_empty). There is no ANDing or ORing, it just uses the f0_blk_stat signal linked to the first datapath.

This might work for you, as long the DMA writes in the datapath linked to f0_empty at last.

Note that:

.f0_blk_stat( { f0_empty, DCMP_dp_f0_blk_stat_3, DCMP_dp_f0_blk_stat_2, DCMP_dp_f0_blk_stat_1 } ), 

is not a function (or module). This is only one of the signals required by the datapath module. Think as a C function with an output argument. It links a signal internally generated by the datapath FIFO to a wire. All these signals are assign internally by the datapath module. Each one is linked to a 8-bit datapath FIFO.

[Len_CONSULTRON]

Rodolfo,

I tried to find where the 'function' .f0_blk_stat is defined.  No luck.

What you said does make some sense.  If the f0_empty signal is generated only on one of the f0_blk_stats this is workable.  It is important to know which one.  Knowing allows for a proper DMA TD to be created to move data into the UDB structure.   

As a byte transfer, the signaling f0_blk_stat would have to be the last byte transferred.

As a word transfer, the signaling f0_blk_stat would have to be the last word transferred. 

[RodolfoGL]

Hi Len,

The ".f0_blk_stat" is not a function, it just one of the signals from the datapath module. You can think like this, if you get to implement something in C to simulate the datapath.

uint8_t f0_blk_stat;
datapath_32bit_run(..., &f0_blk_stat, ...);
printf("%b",f0_blk_stat);

This code would print 00001111 after writing 32-bit to the datapath FIFO. However, if you could print this very quickly (faster than the DMA), you would see: 

00000000

00000011

00001111

Since the DMA don't write 32-bit all at once, only 16-bit.