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Len_CONSULTRON
Level 9
Level 9
500 solutions authored 1000 replies posted 750 replies posted

I have another advanced question involving the UDB Editor.

Can I pass a formal or local parameter set at the symbol level to the UDB editor file (which has a .cyudb file extension)?

The goal is to pass the size of the DataPath into the .cyudb definition.  This will eliminate the need for me to create 4 versions of a .cyudb file with the different Datapath size (ie 8, 16, 24 and 32 bits).

Len
"Engineering is an Art. The Art of Compromise."
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1 Solution
Len_CONSULTRON
Level 9
Level 9
500 solutions authored 1000 replies posted 750 replies posted

To all.

With the help of others and my own research and experiments, I believe I have an answer to my question.

The short answer: Yes.  The UDB Editor can use parameters declared in the symbol file (.cysym) that is associated with the .cyudb file used by the UDB Editor.

The long answer: Not every field in the UDB Editor can accept a parameter.   Specifically the one I wanted to use a parameter to pass to is the DataPath Width.  This field is only selectable as 8, 16, 24 or 32 bits and cannot accept parameters.

A number of the other fields in the UDB Editor that accept an expression can accept the parameter in the form: `=$<param_name>`

An example is given in AN82156_Designing_PSoC_Creator_Components_with_UDB_Datapaths-ApplicationNotes Section 6.4.

Len
"Engineering is an Art. The Art of Compromise."

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RodolfoGL
Employee
Employee
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I don't know the answer when using UDB editor. But you can definitely do it in Verilog by using the generate condition. For example:

generate
   if (CONDITION)
   begin: Option1
      ...
   end
   else
   begin: Option2
   end
endgenerate

You can refer to the ShiftRegister verilog code (BShiftReg_v2_30.v).

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Rodolfo,

I might end up using your suggestion.  I thought about this solution in the past.  It would be a bit cumbersome and not very backwards compatible to the original .cyudb design file.

The sad thing, I was using the UDB editor to help minimize the PSoC resources used for my custom component.  Additionally the use of the State machine logic diagramming is more human readable for logic flow.

The UDB editor creates a Verilog file as a final result.  However, if you look at it, it has a lot of defines to the UDB block registers for configuring.   It is significantly different whether using 8, 16, 24, or 32 bits as a datapath.

Using your suggestion, the easiest way to implement the Verilog conditional compile is to generate a verilog file for each of the 4 widths of datapath.   Place all versions of these Verilog files into one massive Verilog file with the conditional expressions.   Doable but cumbersome especially if changes need to be made at a latter date.

Len
"Engineering is an Art. The Art of Compromise."
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RodolfoGL
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The UDB editor will not help to minimize the PSoC resources. If writing proper Verilog, you will always be better of in terms of hardware resources usage. The UDB editor burns a lot of macrocells to implement the state machines and control signals. 

The UDB editor might be appealing for someone without experience with Verilog. But if you do know how to write Verilog code, that's the way to go!

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Rodolfo,

This might be generally true.  How do you guarantee that the A0, A1, D0, D1, F0 and F1 registers get used properly and efficiently?

By using the UDB Editor, I can guarantee control of these registers which prevents the need of using Control and Status registers which might be allocated by Verilog instead of the UDB Editor.

You might be right about a less efficient allocation of macrocells and P-terms in UDB Editor.  However with careful logic assignment this might be a moot-point.

I propose a challenge to you if you're interested.

I just recently uploaded a new component to "Code Examples": DCmp-component-Very-fast-Digital-Comparisons 

It used the UDB Editor to significantly reduce PSoC resources over a similar Infineon component: Digital Comparator.

I provide a resource list in the component datasheet based on the selected configuration.

The Challenge

Re-code the DCmp component using same functions with Verilog solely.   Let's then compare the results.

Note:  Using the UDB Editor, you can generate a Verilog output as a starting point for your implementation.

To simplify the challenge.   I created 4 sub-components DCmp_thresh2_xxb_v1_1  with 'xx' = 8, 16, 24, and 32 bits.   This is the component I use with UDB_Editor.   If you combine these four into one Verilog with the datawidth parameter we can compare the resources used.

Len
"Engineering is an Art. The Art of Compromise."
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RodolfoGL
Employee
Employee
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Just looking at the Verilog code generated by the UDB Editor, I can see some margin for improvements. For example, the SM_1 state machine use 2 bits, but you could have used only 1 bit, since it has two states only. For this specific case, the logic is very simple, so you might be very close to the optimal usage of the resources. Once you start implementing very complicate state machines to control your datapath, you will definitely be better off using Verilog.

There is no need to use a control and status register to do a comparison. The Infineon Digital Comparator might use this approach to have a tight control by the CPU, but we could have simply used the FIFO status, as you did.

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You are correct.

The first state using 2'b00 is a left-over from a previous revision of this component which had three states.

Changing 2'b00 to 1'b0 is a simple minimization.  However, making the change, I re-assessed the macrocell and Pterm resources used => No Change.   I suspect the Creator fitter program optimized out the 2'b00 down to needing only one bit.

Actually the Digital Comparator uses no Control or Status registers either.   They also don't use datapaths, sort of ...

However, since their data input is HW  'wired' it consumes many macrocells and P-terms which makes these resources unavailable for the UDB blocks that they originally associated with.   Using other components designed to use datapaths may limit placement in the part.

I'm not as strong in Verilog coding.  I've only done some very simple logic codings.   Although my DCmp uses no Control or Status registers either, it does use the UDB registers in place of CRs and SRs.  

Is there a document detailing the use (and naming conventions) of the UDB configuration registers for use in Verilog?  

Len
"Engineering is an Art. The Art of Compromise."
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Len,

Since you already created 8, 16, 24 and 32-bit comparator components, I think it is easy to make one TOP component using schematic, including all 4 component. Then conditionally enable only one of them using  CY_REMOVE parameter, like: !(BitWidth==8).

     Many Creator components are made this way. The drawback is all 4 components must be distributed  along with the Top component, but they can be made hidden in the catalog. 

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/odissey1,

Thank you.  That's exactly how DCmp is created.  You will find a DCmp_v1_1.cysch where this implemented.

As you pointed out, I have 4 versions of the sub-component called DCmp_thresh2_xxb_v1_1 to support each datapath.   However it sucks that if I chose to make a change in one, it has to be make in 3 more.

Yes.  They are configured as "Doc.CatalogVisibilityExpression = false".

Len
"Engineering is an Art. The Art of Compromise."
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Len_CONSULTRON
Level 9
Level 9
500 solutions authored 1000 replies posted 750 replies posted

To all.

With the help of others and my own research and experiments, I believe I have an answer to my question.

The short answer: Yes.  The UDB Editor can use parameters declared in the symbol file (.cysym) that is associated with the .cyudb file used by the UDB Editor.

The long answer: Not every field in the UDB Editor can accept a parameter.   Specifically the one I wanted to use a parameter to pass to is the DataPath Width.  This field is only selectable as 8, 16, 24 or 32 bits and cannot accept parameters.

A number of the other fields in the UDB Editor that accept an expression can accept the parameter in the form: `=$<param_name>`

An example is given in AN82156_Designing_PSoC_Creator_Components_with_UDB_Datapaths-ApplicationNotes Section 6.4.

Len
"Engineering is an Art. The Art of Compromise."