Shift register component: accessing the status register by hardware & question about the load event interrupt

[RaAl_264636]

Hi,

       

I 'm new to PSoC and want to dig deeper into it So I bought a PSoC 4 pioneer kit as a starting point.

   

Now, I want to go for my 'real' first own design. This design uses a shift register component.

       

I've some questions:

   

1) It seems a counter is necessary to detect if the desired number of bits have been shifted, right?

   

2) I want to generate an interrupt if a new byte has been loaded from the FIFO into the shift register. I don't use the load input signal, but it seems that the load interrupt output can still be used for that purpose, right?

   

3) Is it possible to access the shift register status register (or the underlying UDB) by hardware? I want to detect if the FIFO is empty.

       

Regards,

       

Ralf