In the module datasheets you have the following issues -
1) Analog mux, you give a selttling time with out any attached resolution. There
should be a table of times vs resolution to 20 bits, down to 8 bits.
2) S/H, same problem, you only spec to 1% which is ~ 7 bits, not really a useable
number for worst case design. Again a table from 8 to 20 bits.
3) You should show in applicable datasheets how to calc settling time to worst
case for a first order R-C network so users can calc their own design. Calc to 1/2 LSB.
@Nazr: Dana already gave a list of affected components (Sample&Hold, AnalogMux). I guess it affects all devices where these components are available.
Anything in analog signal path that is band limited. I would add OpAmps,
Mixer to the list. The whole conecpt of having a 20 bit A/D, or 12 bit SAR for that
matter, only works right when one does not incur settling time violations
performing measurements resulting in measurement error.
Not to be forgotten would be worst case drift, PSRR effects. Even GBW in OpAmps
contribute to AC measurement errors.
I think a spreadsheet of all potential errors associated with a component should be
created and one by one either specifications be entered or notes guarenteed by
The reason we buy test instrumentation from Agilent and Tek and Keithley and Marconi
and....is they have done all this worst case analysis in their designs to back up their specs.
Otherwise their competitors would quickly point out their 8.5 digit DVM is really only a
4 1/2 digit and destroy their customer base confidence.