See generated Verilog ?

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HuEl_264296
Level 5
Level 5
First like given 25 sign-ins First solution authored

Hi all,

   

 

   

When I place a digital component, and build the project, does that component generate a Verilog file ?  Is it possible to see this verilog file ?

   

 

   

Many thanks

   

Hugo Elias

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