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I'm using PSoC creator 4.3 and PDL 3.1.3
I created an SPI block as a master (see screen shot). There are two slave devices, one is write-only and a data width of 9 bits. The other is read-only and has a data width of 11 bits.
According to the UDB editor, if the Tx and Rx data widths are not the same, you have to use the "National Semiconductor" sub mode.
I selected "National Semiconductor" and it built fine. However, when I run the code, during SPI initialization there is an exception generated by an ASSERT which checks if "National Semiconductor" mode is selected when the Tx/Rx sizes are different. I found that the reason for this assertion is that for some reason, the generated SPI config code does NOT set sub-mode to "CY_SCB_SPI_NATIONAL", but instead uses "CY_SCB_SPI_TI_COINCIDES". (see code snippet below)
I'd like to know if this is a bug, or if I am doing something wrong.
cy_stc_scb_spi_config_t const SPI_DISPLAY_config =
{
.spiMode = CY_SCB_SPI_MASTER,
.subMode = CY_SCB_SPI_TI_COINCIDES,
.sclkMode = CY_SCB_SPI_CPHA0_CPOL0,
.oversample = 16UL,
.rxDataWidth = 11UL,
.txDataWidth = 9UL,
.enableMsbFirst = true,
.enableInputFilter = false,
.enableFreeRunSclk = false,
.enableMisoLateSample = false,
.enableTransferSeperation = false,
.ssPolarity = ((((uint32_t) CY_SCB_SPI_ACTIVE_LOW) << SPI_DISPLAY_SPI_SLAVE_SELECT0) | \
(((uint32_t) CY_SCB_SPI_ACTIVE_LOW) << SPI_DISPLAY_SPI_SLAVE_SELECT1) | \
(((uint32_t) CY_SCB_SPI_ACTIVE_LOW) << SPI_DISPLAY_SPI_SLAVE_SELECT2) | \
(((uint32_t) CY_SCB_SPI_ACTIVE_LOW) << SPI_DISPLAY_SPI_SLAVE_SELECT3)),
.enableWakeFromSleep = false,
.rxFifoTriggerLevel = 0UL,
.rxFifoIntEnableMask = 0x0UL,
.txFifoTriggerLevel = 0UL,
.txFifoIntEnableMask = 0x0UL,
.masterSlaveIntEnableMask = 0x0UL
};
Solved! Go to Solution.
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Erja,
Because you have an urgent need, I've attached a 'replacement' for the SCB_SPI_PDL component.
The replacement has the 'fix' mentioned above.
To use it, just unarchive it and drop the directory into the directory of your project. Since the component has the same name as the component you're correcting, the component in TopDesign needs NO CHANGES. You should be able to Application build and find the desired subMode to be as you were expecting.
WARING!!! This changed component has NOT BEEN TESTED! Use it at your own risk.
Len
"Engineering is an Art. The Art of Compromise."
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Erja,
I have confirmed your results.
Note: If you change to Mode = Slave, Sub Mode = National then .
subMode = CY_SCB_SPI_NATIONAL,
I tried to identify if Mode = Master is allowed to have Sub Mode = National.
The issue comes up in the SCB_SPI_PDL.c file.
.subMode = `= (0 == $SubMode) ? "CY_SCB_SPI_MOTOROLA" : (1 == $Mode) ? "CY_SCB_SPI_TI_COINCIDES" : (2 == $Mode) ? "CY_SCB_SPI_TI_PRECEDES" : "CY_SCB_SPI_NATIONAL"`,
The following is more for Cypress. If the above code is changed to:
.subMode = `= (0 == $SubMode) ? "CY_SCB_SPI_MOTOROLA" : (1 == $SubMode) ? "CY_SCB_SPI_TI_COINCIDES" : (2 == $SubMode) ? "CY_SCB_SPI_NATIONAL" : "CY_SCB_SPI_TI_PRECEDES"`,
then the subMode can be changed to match the Sub Mode set in the configuration panel in either MASTER or SLAVE modes.
Len
"Engineering is an Art. The Art of Compromise."
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Erja,
Because you have an urgent need, I've attached a 'replacement' for the SCB_SPI_PDL component.
The replacement has the 'fix' mentioned above.
To use it, just unarchive it and drop the directory into the directory of your project. Since the component has the same name as the component you're correcting, the component in TopDesign needs NO CHANGES. You should be able to Application build and find the desired subMode to be as you were expecting.
WARING!!! This changed component has NOT BEEN TESTED! Use it at your own risk.
Len
"Engineering is an Art. The Art of Compromise."
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Hi Len,
Thank you VERY much for your prompt reply and solution!
In the meantime, I actually changed my strategy as an interim workaround by re-initializing the SPI block with a different transfer size for the times. The overhead in doing this is acceptable for my current purpose (and it's just a workaround until a new spin of hardware.) I will keep your special UDB on hand, though as an alternative approach.
Again, I really appreciate your great support!
Best regards,
Eric Jappe
On Saturday, December 12, 2020, 8:20:14 AM EST, LePo_1062026 <community-manager@cypress.com> wrote:
|
Cypress Developer Community |
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SPI "National Semiconductor" sub-mode does not work (urgent!)
reply from LePo_1062026 in PSoC Creator & Designer Software - View the full discussion
Erja,
Because you have an urgent need, I've attached a 'replacement' for the SCB_SPI_PDL component.
The replacement has the 'fix' mentioned above.
To use it, just unarchive it and drop the directory into the directory of your project. Since the component has the same name as the component you're correcting, the component in TopDesign needs NO CHANGES. You should be able to Application build and find the desired subMode to be as you were expecting.
WARING!!! This changed component has NOT BEEN TESTED! Use it at your own risk.
Len
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Erja,
You're very welcome.
Len
"Engineering is an Art. The Art of Compromise."