SPI. Relationship between Tx FIFO, Tx Buffer, Rx FIFO & Rx Buffer

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DaCh_4286001
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I am confused with the relationship between Tx FIFO, Tx Buffer, Rx FIFO & Rx Buffer. Please correct me if my understanding of this is incorrect.

In SPI, I am sending data from master to slave.

Data (suppose 10 characters) from master will be filled into Tx Buffer. Then it will move into Tx FIFO, which in hardware is 4 bytes. Then the data will be received by slave in Rx FIFO, move into Rx Buffer and being saved. After all data being received (Rx FIFO Empty), Rx Buffer size should be 10 because I transmitted 10 characters

Simon

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I was not aware that master and slave were on the very same chip. Your project shows that.

When you remove the delays in your interrupt handler all runs well.

As a rule of thumb: Do not use delays or wait-loops within an interrupt handler. Keep handlers short. When applicable just set a (volatile) flag and act upon that in the main-loop.

Another solution would be to set the interrupt priority of your handler to the lowest, so it might get interrupted by all others. >Give it a try.

Happy coding

Bob

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