This post is meant to distribute the first order DeltaSigma modulator component constructed from the SC/CT blocks. This component exposes the useful DeltaSigma modulator functionality of the SC/CT blocks in an easy to use way. Provide a clock (5 Khz to 4 Mhz), a reference (the 1.024 volt SC/CT block reference is the only suitable reference that does not require buffering) and an analog input in order to use the modulator. The component also exposes the integrator reset for incremental mode, as well as the analog output of the integrator for educational or creative purposes. There is currently no datasheet for the component, but all that is required is to call the _Start() API in order to use the modulator.
The modulator has 2 input ranges. Vref +/- 2*Vref and Vref +/- 0.5*Vref. When using the 1.024 reference, the modulator input ranges are 0 – 3.072 volts and 0.512 – 1.536 volts.
Rev *A: The component now correctly handles different clock sources and low voltage boost pump operation. Please use this version.
This component is not "complete" in the sense that it does not contain a datasheet, but since I am not sure when I will get around to generating a datasheet for this component and it has value even with a half-finished set of documentation, I am releasing it anyway. The zip archive includes an breif description of the component and the connections, a .cycomp archive of the component, and a bundle example project.
Many thanks this is great component - very usefull for me !
My one question - is possible make simple verilog 8bit demodulator ? (for controlling other verilog components)
Many thanks info
You can look at Kees' 'UDB Single Bit IIR Filter' component: http://www.cypress.com/?app=forum&id=2492&rID=76870 . There is also a 2nd order CIC decimator available, but it delivers 16 bit results (even though the usable resolution is only about 10 bits): http://www.cypress.com/?app=forum&id=2492&rID=76872
No no this is not verilog !
Only simple 8bit verilog demodulator like "reverse pwm" (one input mod source from analog modulator - and one 8bit output for controlling other verilog components )
@jls1: So with "verilog" you meant "without using the path, just the PLD part of the UDB"? This might be possible, but it would miss the point of using the PSoC... For pure Verilog, I think google will help you.
Yes only simple PLD. Is possible make example verilog code ? I looked on the internet and I could not find anything like it.
Many thanks Kamil
Today im working on simple 8bit demodulator.
module DeMod8(din, en, clk, rst, dout);
input en, rst, clk;
output [7:0] dout;
reg [7:0] dout;
reg [2:0] cnt;
always @(posedge clk) begin
dout = 0;
cnt = 0;
end else if (en) begin
0:dout = din;
1:dout = din;
2:dout = din;
3:dout = din;
4:dout = din;
5:dout = din;
6:dout = din;
7:dout = din;
cnt = cnt + 1;
This verilog code working fine but not precise.
Please help me with more precise code - many thanks