I have a register that outputs a bus with 8 signals on it. This goes to a two terminal AND gate which outputs to 8 different GPIO pins.
How can I get the output of the PWM UDB block to drive the other Bus input on the AND Gate?
Solved! Go to Solution.
Attached is a custom component which accomplishes exactly same function which you requested (Control_Reg + AND gate). The component is made in Verilog, and performs following function:
outp[7:0] = inp x Value.
Demo project is attached. To manipulate output at run-time, use component API:
Scale_1_SetValue(value); // value = 0 to 255.
To import component from the demo project, please follow standard steps outlined in this tutorial:
Figure 1. Example of selectively passing PWM output to 8 pins.
Figure 2. Example of controlling VDAC amplitude using Scale_1_SetValue() API.