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PSoC™ Creator & Designer Forum Discussions

MiBr_1434631
Level 1
Level 1
First like received

I have a register that outputs a bus with 8 signals on it. This goes to a two terminal AND gate which outputs to 8 different GPIO pins.

How can I get the output of the PWM UDB block to drive the other Bus input on the AND Gate?

pastedImage_0.png

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1 Solution
NoriakiT_91
Employee
Employee
100 likes received 50 likes received 25 likes received

This could be a solution.

GS004341.png

Regards,

Noriaki

View solution in original post

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3 Replies
NoriakiT_91
Employee
Employee
100 likes received 50 likes received 25 likes received

This could be a solution.

GS004341.png

Regards,

Noriaki

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That's a really clever work around

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

MiBr,

Attached is a custom component which accomplishes exactly same function which you requested (Control_Reg + AND gate). The component is made in Verilog, and performs following function:

outp[7:0] = inp[0] x Value.

Demo project is attached. To manipulate output at run-time, use component API:

Scale_1_SetValue(value); // value = 0 to 255.

To import component from the demo project, please follow standard steps outlined in this tutorial:

https://www.cypress.com/video-library/PSoC/psoc-creator-tutorial-importing-components/107756

/odissey1

Figure 1. Example of selectively passing PWM output to 8 pins.

BusScale_01a_A.png

Figure 2. Example of controlling VDAC amplitude using Scale_1_SetValue() API.

BusScale_01a_B.png

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