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I'd start by looking at the generated assembly listing and comparing them, to get an understanding of why the (char) program needs more flash than the (unsigned int) version.
My guess would be down to byte alignment and pointer sizes or CPU Instructions. It might take the core CPU more instructions to move 8-Bit signed chars about, than it does unsigned ints. Thus resulting in a larger program.
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In fact, is is indeeed that the core CPU requires more instructions to move signed chars then unsigned ints.
Here is the compiler output of both versions of test(...) for you to compare:
15:.\main.c **** unsigned int test(unsigned int dat)
16:.\main.c **** {return dat+1;}
27 .loc 1 16 0
28 .cfi_startproc
29 0000 80B5 push {r7, lr}
30 .cfi_def_cfa_offset 8
31 .cfi_offset 7, -8
32 .cfi_offset 14, -4
33 0002 82B0 sub sp, sp, #8
34 .cfi_def_cfa_offset 16
35 0004 00AF add r7, sp, #0
36 .cfi_def_cfa_register 7
37 0006 7860 str r0, [r7, #4]
38 .loc 1 16 0
39 0008 7B68 ldr r3, [r7, #4]
40 000a 0133 add r3, r3, #1
41 000c 181C mov r0, r3
42 000e BD46 mov sp, r7
43 0010 02B0 add sp, sp, #8
44 @ sp needed
45 0012 80BD pop {r7, pc}
46 .cfi_endproc
15:.\main.c **** char test(char dat)
16:.\main.c **** {return dat+1;}
27 .loc 1 16 0
28 .cfi_startproc
29 0000 80B5 push {r7, lr}
30 .cfi_def_cfa_offset 8
31 .cfi_offset 7, -8
32 .cfi_offset 14, -4
33 0002 82B0 sub sp, sp, #8
34 .cfi_def_cfa_offset 16
35 0004 00AF add r7, sp, #0
36 .cfi_def_cfa_register 7
37 0006 021C mov r2, r0
38 0008 FB1D add r3, r7, #7
39 000a 1A70 strb r2, [r3]
40 .loc 1 16 0
41 000c FB1D add r3, r7, #7
42 000e 1B78 ldrb r3, [r3]
43 0010 0133 add r3, r3, #1
44 0012 DBB2 uxtb r3, r3
45 0014 181C mov r0, r3
46 0016 BD46 mov sp, r7
47 0018 02B0 add sp, sp, #8
48 @ sp needed
49 001a 80BD pop {r7, pc}
50 .cfi_endproc
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All this means is that the CPU is optimized to work with 16-Bit ints, rather than 8-Bit chars.
In my tests it made no difference if the char was signed or unsigned.
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Thank you very much for the detailed explanation!
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I assume you have seen this -
http://www.cypress.com/?rid=91945 AN89610 - PSoC® 4 and PSoC 5LP ARM Cortex Code Optimization
Regards, Dana.