How to make a counter that latches high?

JoBr_1593366 · ‎Sep 02, 2021

The Counter datasheet (PSoC3) says

"Run Mode … One Shot – The Counter runs through a single period and stops at terminal count. … On stop, … for a fixed-function counter, the count register remains at terminal count."

"tc … goes high one clock cycle after the count value matches the terminal count and stays
high while the count value is equal to the terminal count."

So I would think that the tc output is low until it counts down to 0 (the terminal count) at which point the output switches to high, but in reality it only pulses high at that point and then goes low again, with these settings:

So I tried to latch it with an RS flip-flop, but it complains about "asynchronous clock domain crossing" and doesn't seem to work reliably.

So I tried to use an asynchronous DFF to latch instead, but it complains about 'Control signal "dsrff(clock)" driving signal "Net_3998" is always "low".'

Is there some better way?

BiBi_1928986 · ‎Sep 04, 2021

Hello.

I did this with a PSoC 4. I connected the counter OV output to the clk input of DFF. Connect a '1' to the D input. I used a Control Register component to reset the DFF (with AR on symbol). Otherwise, you can't reset the DFF back to 0.

For your application, connect TC to the DFF clk input, etc. I expect this will also work with PSoC 3.

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How to make a counter that latches high?

How to make a counter that latches high?

Re: How to make a counter that latches high?