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PSoC™ Creator & Designer Forum Discussions

Anonymous
Not applicable

Hello PSoCers     

   

I am willing to submit this article.     

   

Still getting started this component division.     

   

i am afraid of some rudeness of mine.     

   

don't know the rule of this division yet.     

   

     

            

   

In my practice, DDS module become working.     

   

There are many items to have improvements.     

   

I want to listen to how to get more efficiency.     

   

Want to listen to critique from everyone     

   

     

            

   

I have been work with Xilinx CPLDs,     

   

those works are mainly schematic-base design.     

   

I am new to PSOC CPLD and Warp-Verilog.     

   

     

            

   

Keep it up rolling !     

1 Solution
Anonymous
Not applicable
        I would describe easy operation of test bench.   
This is using PSoC5LP on P4 Pioneer Kit as bootloadable device.   
   
It is very simple.   
1) Connect the USB cable while pressing the SW1:reset button   
The status LED(green) start blinking   
2) When load the program: Use /Tools/Bootloader Host   
instead of PSoC Programmer.   
3) Ensure Port Filters, USB Device: VID=0x04B4 PID=0xF13B   
4) Load bootable object [P5LP_DDS.cyacd] from MortexM3 directory, And write it.   
5) Ensure the Jumper plug J13 to ON   
If not, Pioneer Kit return to bootable status every time.   
   
If you are using without Pioneer KIt,   
Change project setting, Code Generation/Application type to "Normal" and Need to some refine cydwr, System Setting.   
   
When you want to revert default setting of Pioneer Kit   
It is also easy, PSoC programmer doing that.   
   
In detail, See user guide of Pioneer Kit, section 6: Advanced Section   
Regards.   

View solution in original post

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42 Replies
Anonymous
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 This is the component export 

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Anonymous
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Anonymous
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Anonymous
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Frequency range : 1mHz to 10KHz (sine wave)

   

Frequency resolution : 1mHz nominal

   

Test design is work with PSoC5LP in PSoC4 Pioneer Kit

   

(bootable composition) 

   
        
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Anonymous
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 I was using Creator2.2 sp1 

   

Because 3.0 intelligent helper has trouble in component design,

   

Treat of Instance name space.

   

However that seems working well finally. 

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HeLi_263931
Level 8
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Level 8

I can confirm it at least compiles in Creator 3.0.

   

What is the difference to the DDS project of PSoC Sensei? Your component seem to have simpler setup, but creates only sine waves.

   

What is the frequency step resolution your DDS component achieves? Is it 'DDS frequency / 2^32' (the verilog looks like your are using a 32 bit phase accumulator)?

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Anonymous
Not applicable
        I would describe easy operation of test bench.   
This is using PSoC5LP on P4 Pioneer Kit as bootloadable device.   
   
It is very simple.   
1) Connect the USB cable while pressing the SW1:reset button   
The status LED(green) start blinking   
2) When load the program: Use /Tools/Bootloader Host   
instead of PSoC Programmer.   
3) Ensure Port Filters, USB Device: VID=0x04B4 PID=0xF13B   
4) Load bootable object [P5LP_DDS.cyacd] from MortexM3 directory, And write it.   
5) Ensure the Jumper plug J13 to ON   
If not, Pioneer Kit return to bootable status every time.   
   
If you are using without Pioneer KIt,   
Change project setting, Code Generation/Application type to "Normal" and Need to some refine cydwr, System Setting.   
   
When you want to revert default setting of Pioneer Kit   
It is also easy, PSoC programmer doing that.   
   
In detail, See user guide of Pioneer Kit, section 6: Advanced Section   
Regards.   
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Anonymous
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        Haw! I am becoming The Invisible Man   
I like it.   
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Anonymous
Not applicable

 Great project many thanks 🙂

   

 

   

Please help

   

 

   

When compile with Creator 2.2 SP6 working great but this peoject open and recompile with Creator 3.0 not working (compilling without errors but bootloader not working only fast blinking programming led)

   

 

   

Thanks help.

   

 

   

Kamil

Anonymous
Not applicable
        Hello JLS1 welcome   
Basically, this was working on my Creator3.0   
But I worry about some error display at component design.   
I was publish on Creator2.0   
So, I have a Creator 3.0 version, I can be uploading.   
But please wait for awhile, I have to ensure the bootloading   
and Upload it tommorow.   
Thank you.   
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Anonymous
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        Hi   
You won't wait any longer.   
I confirmed bootloading that Creator3.0 version.   
Try customize it, improve it and talking here   
This is it.   
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Anonymous
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 PSoC73 very thanks quick response 🙂

   

 

   

Today night im testing.

   

 

   

Kamil

Anonymous
Not applicable

Created 3.0 version tested and working !

   

 

   

Many thanks this great component.

   

 

   

Kamil

Anonymous
Not applicable
        Thank you   
I wish many person to use it for various applications   
Nonetheless, It is up to 10KHz or 20KHz around.   
Regards.   
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Anonymous
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        Hi JLS1   
Don't be worry someone said like a "This is a copy of something"   
To say such a thing without showing the evidence,   
They must be not civilized people.   
   
I can prove but I wouldn't say.   
Strange person is every time,   
Rotten egg is every where.   
Thank you.   
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Anonymous
Not applicable
        Hello I got success to manage the sine table on the Verilog and UDBs.   
The DDS that is independent from the CPU, has completed the operation   
This time, It could be extended to the maximum frequency up to 200KHz.   
   
Verilog is a concept of layout design completely different from the stored program conception.   
Which had a tough time too much consume macro-cells in the place   
where the unexpected.   
   
It will be upload, soon.   
Regards.   
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Anonymous
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 Great news thanks info 🙂

Anonymous
Not applicable
        This is Creator3.0 version   
Regards   
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Anonymous
Not applicable

      

   

Hello everyone     

   

The latest old version had manage the sine-table handling by ISR     

   

So, It was late, upto 10KHz, max clock is 500KHz.     

   

[ How to use Verilog table and DMA? ]     

   

That was super tough questions for me.     

   

The Warp-Verilog don't allow using ROM table or SRAM table.     

   

Last night I red the book of Verilog and find a solution.     

   

function and case statement will do this !     

   

      

   

Hence, i had work for it on this weekend.     

   

Nonetheless, the road was winding.     

   

Barely, I could be reduce consumptions of UDBs within PSoC's     

   

Anyway, this is it.     

   

More improvements will comming later.     

   

Thank you.     

   

      

   

Wave Form [click to enlarge]      

   

              https://63c5fc03-a-62cb3a1a-s-sites.googlegroups.com/site/flathill73/pix_page/dds_photo.jpg      

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Anonymous
Not applicable
        I have a small revise to the circuitry.   
Due to I am overlooking the iDAC has a direct drive bus.   
Still, DDS clock is stay at 4MHz   
This is maximum, I guess.   
Thank you   
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Anonymous
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Hi PSoC73

   

 

   

Im made simple FM synthesizer example from your modified component.

   

 

   

Connect headphone or oscilloscope to pin P3[0] (VDAC output)

   

 

   

Thanks your work

   

 

   

Kamil

Anonymous
Not applicable
        Man JLS1, Super Great!   
What a Hella of wonderful !   
First time, I saw the wave form and say OK, but not the end.   
Next, I connect to the Speaker!   
How to do it !   
I didn't understand how works   
   
Very low tone sound is nice   
I hadn't imagine DDS can do that   
   
Thank you very much   
If you have another tune, Please Please   
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Anonymous
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        Hey JLS1   
I'm watching your main.c   
I'm searching for the musical score   
...   
How to do this magic?   
...Two rand() !   
I never believing.   
...PSoC sing this song !   
I do not want to believe   
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Anonymous
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        Upload the RAW Video   
Must See   
[ http://www.youtube.com/watch?v=xgxNmvok4go ]   
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EvPa_264126
Level 7
500 replies posted 250 replies posted 100 likes received
Level 7

I added a keypad 4x4.
It was a good sine/rectangle generator for me.
Thanks for component.
 

Anonymous
Not applicable

Simple FM and Additive algoritmic synthesizer 🙂

Anonymous
Not applicable
        How's This?   
More Addictive   
More Passionate   
I CAN'T STOP !   
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Anonymous
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        Thank you povloven   
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Anonymous
Not applicable
        More Random   
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Anonymous
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Anonymous
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        Hey JLS1   
I had do RANDOMIZE the analog circuit.   
Please Infusing your magical idea.   
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Anonymous
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Hi PSoC73

   

 

   

Nice sound and nice modification 🙂

   

 

   

Thanks Kamil

Anonymous
Not applicable
        Hello JLS1   
This time, I was made additionally communication device.   
This can be control from PSoC4 capsense sliders.   
Tempo, Tone, Strength? can control by sliders   
It is still very basic composition now,   
We may more study about DDS-FM.   
   
1) Slider value send to PSoC5LP   
2) Push button status will send   
3) While push Button and slid, Slider2 value will send   
4) P5 header P0-0 is assign to Debug print out   
you can read parameters value by LCD or Hyper Terminal.   
   
I wish you will be find more magical Trans Music   
Thank you.   
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Anonymous
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Anonymous
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Bob_Marlowe
Level 10
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Level 10

@PSoC73

   

Well, I am playing an instrument and to be honest: Besides the rythm in your PSoC performance the music sounds as if I stepped on one or more of my cat's tail(s). I'll give you a hint (takes some math) how to improve the melodity dramatically:

   

You know (although it does not sound so ) that we have a twelve-tone music with 12 evenly separated tones with a simple numerous dependency. Since one "oktave" (which consists of 12 notes, not 😎 has the frequency doubled, thus with 12 notes each is member of a geometric progression with the factor 12th root of 2. Starting with a at 440Hz (or 110Hz) wihich is the frequency of the (low) chamber pitch "a", you could generate a row of exact tones.

   

Now the trick:

   

When you exclude allo the full-tones (c,d,e,f,g,a,h) only 5 tones remain. Playing music with random notes out of this 5 will always (at least for occident ears) sound melodiously. You can prove this effect by playing only the black pianokeys randomly.

   

 

   

Bob

Anonymous
Not applicable
        Ah, Thank you very much for great Music Theory.   
Please give me the lecture of harmony and chord progression, next time.   
Now, Im tried to 3 voice synthesiser but   
that impossible from UDBs max number limit.   
So, I'd trying to do envelope control of tones.   
Please take looking forward   
Regard   
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Bob_Marlowe
Level 10
First like given 50 questions asked 10 questions asked
Level 10

For envelope: ja.wikipedia.org/wiki/ADSR in Japanese, for all other interested members: look for "ADSR" at wikipedia, didn't find an english entry.

   

 

   

Bob