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How can I create basic OR logic gate by HW with CY8C4147LQE-S443 and output to pin P6[1]?
It looks like there is no UDB implemented and Smart I/O doesn't support Port 6.
Thanks.
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brlo,
Even if you had UDB or SmartIO support on the port pin, these features are not operational in low-power modes.
If the wired OR scenario wont work for in your design, you will have to consider ISRs on the OR inputs to provide a HW-equivalent in SW.
"Engineering is an Art. The Art of Compromise."
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brlo,
You are correct. user-designed logic such as a OR function is not supported on Port 6[1] on the PSoC4100s Plus device you have selected.
There are NO UDBs and SmartIO is only available on ports 1, 2, and 3.
Recommendations:
#1
Change to a different part. Obvious but I'm assuming there may not be a close match in other features.
#2
Change to a different port pin. Apparently an OR function should be achievable on any of the pins on ports 1, 2 or 3.
#3
Use an additional pin and 'wire-OR' the pins together. For a wire-Or configuration each of the pins needs to be configured as open-drain drives high. The external pull-down resistor can be a medium value if the output frequency is not to high. It needs to be a lower value if a faster switching speed is needed.
"Engineering is an Art. The Art of Compromise."
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Thanks Len for reply. Unfortunately the change of PCBA design and components is not possible anymore. So only way is to replace HW design of signal generation to SW design, which will increase CPU consumption by interrupts handling.
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brlo,
Even if you had UDB or SmartIO support on the port pin, these features are not operational in low-power modes.
If the wired OR scenario wont work for in your design, you will have to consider ISRs on the OR inputs to provide a HW-equivalent in SW.
"Engineering is an Art. The Art of Compromise."