Forum input requested: New custom Counter component feature set ideas!

[Len_CONSULTRON]

Hi,

I've created a new custom counter component that I haven't officially published yet.   I'm waiting to see if there are any good feature add suggestions.

The component currently functions as a simple up-counter with the following features over the standard counter component:

• A settable maximum value.  (This is virtually identical to the period value)
• A settable reset value.  This allows from non-'0' reset values to be used.   This is useful to create 'signed' value outputs where the reset value can be set to -32768 and the maximum value to 32767 so that the counter will increment from the lowest signed 16-bit value through the highest signed value.
• A settable increment value.  This allows for stepping the count value in values greater than 1.  For example, the counter is 32-bits in width.   If I want to count from 0 to (2^32)-1 with a 48MHz count clock, it would take 89.5 seconds to complete.  Using a increment of 2 would cut this down to 44.8 secs.
• The current counter value doesn't require a two-read operation as with the standard counter.  The counter value is directly readable for DMA access.

Your suggestions for additional features are welcome.

[odissey1 · Accepted solution]

Len,

It would be nice to have digital output bus option. That would allow using the counter in digital design also. For example, the BasicCounter  and Count7 do have such bus. Unfortunately, Count7 is limited to 7 bits only, and BasicCounter consuming too much PLD resources for large Width. 

[Len_CONSULTRON]

/odissey1,

Digital Output Bus: Very good suggestion.

How do we create one where I can move data from a UDB register to a output Digital bus without massive consumption of UDB resources due to the routing requirements?

I imagine this would be the same dilemma in creating a Digital Input Bus interface to the UDB registers.

I don't think the DBUS_IN or DBUS_OUT will be practical using the UDB_Editor.

Maybe with UDB register access in Verilog, this 'might' be possible?

If we can come up with a solution this might have application as a sub-component to use in higher-level components.   If it has a low-resource impact ... even better.

The reason I created the DCmp component is the low resource count so that it can fit in tight PSoC designs or used with multiple instances.  The dominant elements in the DCmp design are the 6 UDB registers that can be linked datapaths in place of Control and Status registers.  However it takes another HW device (DMA) to move data into them,  Hence the 8 to 10 BUS_CLK cycle latency.

[odissey1]

Len,

I will send you some examples of the bus input/output to UDB over weekends. I believe it has to be done in Verilog only, but it relatively easy by enabling some 'dynamic' bit in UDB table, and should consume no extra resources. The bus input, however, takes 1 extra clock to read the bus.  

[Len_CONSULTRON]

/odissey1,

Much appreciated!   It's always good to learn something new!

[AlenAn14]

Hi ,

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Thanks and Regards,
Alen