Datapath ALU input from Parallel Input (not A0 or A1)

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crcac_264396
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Hi,

   

I am trying to learn the datapath, verilog and the configuration tool.

   

I can't work out how to get an input to the ALU from the parrallel in routed fabric. According to the PSoC 5 TRM, fig 23-6 (p.154)  and fig 23-25 (p170) there is a way to source the A input to the ALU from the parallel input routing. I've enabled CFB EN in the CFGRAM, and then selected PI SEL to PIN (register CFG15-14). What I can't work out is I never see PI in the drop down for SRCA in the CFGRAM section. Do I have to manually change it in the verilog file?  I have not been able to guess what the value is (e.g. `CS_SRCA_A0 is obviously A0).

   

Thanks in advance.

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Anonymous
Not applicable

Hello,

   

SRCA input to the ALU can come from either accumulator registers or Parallel In from routing fabric. The Accumulator selections are available in the SRCA dropdown for each of the 8 configuration selection of CFGRAM section in the Datapath tool.

   

The Parallel In (PI) can be selected as input to ALU either statically or dynamically (PSoC 5 TRM Fig 23-25, pg 170). The static operation involves setting the PI SEL bit to PIN (CFG15-14) in the Datapath configuration tool. This forces the ALU ASRC to be PI for all 8 configurations in the CFGRAM section of the datapath tool. The dynamic operation involves enabling the CFB EN bit in the CFGRAM section and enabling PI DYN bit in CFG15-14 of the datapath tool. The CFB EN bit is set on each of the 8 configurations available in CFGRAM section.

   

Note the SRCA input drop down selection in the CFGRAM section will have no bearing on the SRCA input if PI SEL or PI DYN (with CFB EN bit set) is enabled to use Parallel In selection. You can verify the selections by looking at the verilog file generated by the Datapath Configuration tool. For example, the verilog file will indicate an Accumulator or PI selection by the following line - 

   

Accumulator Selection - `SC_A0_SRC_ACC

   

PI Selection  -`SC_A0_SRC_PIN

   

--Sathya

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Anonymous
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Please note that the dynamic Parallel Input operation is not supported with PSoC 5.

   

Sathya

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crcac_264396
Level 4
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 Please note that the dynamic Parallel Input operation is not supported with PSoC 5.

   

Sathya

   

 

   

Thanks for your answers. 

   

 

   

to clarify:

   

for PSoC 5 it is not possible to use the  PI dynamic operation as indicated in the TRM?

   

 

   

therefore, in order to use parallel input do I have to select the CFB EN bit in all 8 configurations for the CFGRAM? 

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OlPe_282281
Level 2
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Welcome! 10 replies posted 5 replies posted
 sath posted on 24 Aug 2012 01:40 PM PST
Cypress Employee
4 Forum Posts
 
 
   

Please note that the dynamic Parallel Input operation is not supported with PSoC 5.

   

Sathya

   

 

   

where do you have this information from? This would be really silly for me

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Bob_Marlowe
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Is the PI supported in PSoC5LP ?

   

 

   

Bob

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Anonymous
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    The engineering samples of PSoC 3 and the production PSoC 5 devices had the original UDB architecture and it had limited usage for parallel in.  In these chips if you used parallel in, then there was little that you could do since the A input to the ALU would always be the Parallel In signal.  This was understood as a limitation and for the production version of PSoC 3 and for PSoC 5LP the UDB was updated to make Parallel In a dynamically switchable feature.  The other significant new feature added with the PSoC 3 / 5LP version of the UDB is the ability to set a FIFO up so that it can be both read and written by the UDB.  This can provide some much needed storage for some applications.  Previously one side of a FIFO must be connected to the UDB and the other side to the CPU.   
   

Sathya

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Bob_Marlowe
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Thx, Sathya!

   

 

   

Bob

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Anonymous
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need a proof, that psoc5 is different from psoc5lp when it comes to datapath parallel in: TRM for both families shows that datapath part is identical. 

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Anonymous
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 what are you asking? I think I saw some info on here that said/implied that the PI was broken/unusable on the psoc5. I joined the psoc world starting with the psoc5lp. I can verify that it works on it. We use it for an 8bit parallel bus using dma for high speed interprocessor communication on some distributed processor designs in several of our products. Do you need to see a working verilog?

   

 

   

Ed

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Anonymous
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is there any errata sheet? I could not find any. 

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Anonymous
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well, if it's interesting to somebody -- according to "square root computation", the difference between psoc5 and psoc5lp is registers fifo. it doesn't work or exist in psoc5.

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